Advanced Hardware Design for Error Correcting Codes

Inbunden, Engelska, 2014

1 122 kr

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Beskrivning

This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book’s chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering.• Examines how to optimize the architecture of hardware design for error correcting codes;• Presents error correction codes from theory to optimized architecture for the current and the next generation standards;• Provides coverage of industrial user needs advanced error correcting techniques.Advanced Hardware Design for Error Correcting Codes includes a foreword by Claude Berrou.

Produktinformation

Utgivningsdatum:2014-11-11
Mått:155 x 235 x 17 mm
Vikt:477 g
Format:Inbunden
Språk:Engelska
Antal sidor:192
Upplaga:2015
Förlag:Springer International Publishing AG
ISBN:9783319105680

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Mer om författaren

Cyrille Chavet is an Associate Professor at Associate Professors at Université de Bretagne Sud, Lorient, France. Philippe Coussy is an Associate Professor at Associate Professors at Université de Bretagne Sud, Lorient, France.

Innehållsförteckning

User Needs.- Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding.- Implementation of Polar Decoders.- Parallel architectures for Turbo Product Codes Decoding.- VLSI implementations of sphere detectors.- Stochastic Decoders for LDPC Codes.- MP-SoC/NoC architectures for error correction.- ASIP design for multi-standard channel decoders.- Hardware design of parallel interleaver architecture: a survey.