VLSI Physical Design: From Graph Partitioning to Timing Closure

Andrew B. Kahng is Professor of CSE and ECE at UC San Diego, where he holds the endowed chair in High-Performance Computing. He has served as visiting scientist at Cadence (1995-1997) and as founder, chairman and CTO at Blaze DFM (2004-2006).Jens Lienig is Professor of Electrical Engineering at TU Dresden. He is also the director of the Institute of Electromechanical and Electronic Design at TUD. He has worked as project manager at Tanner Research, Inc. (1996-1999) and Robert Bosch GmbH (1999-2002).Igor L. Markov is a Professor of Electrical Engineering and Computer Science at the University of Michigan. He has worked at Google (2014-2017) and has been with Facebook since 2018. Jin Hu was a PhD student at the Computer Science and Engineering (CSE) Division at the University of Michigan. Afterwards, she has been with IBM Corp. (2013-2017) and Bloomberg L.P.

This book covers the basic algorithms underlying all physical design steps and also shows how they are applied to current instances of the design problems. It will serve the EDA and design community well. It will be a foundational text and reference for the next generation of professionals who will be called on to continue the advancement of our chip design tools. Dr. Leon Stok, Vice President, Electronic Design Automation, IBM Corp -------- A clear sign of when a field matures is the availability of a widely accepted textbook. Finally, there is a well-balanced textbook that introduces the key components of a layout synthesis flow with sufficient depth and an eye for the context in which they are used. It lucidly presents what any maker of chip design tools should have as a core foundation. Prof. Ralph H.J.M. Otten, Technical University of Eindhoven ------- This is the book I wish I had when I taught EDA in the past, and the one I'm using from now on. Dr. Louis K. Scheffer, Howard Hughes Medical Institute ------- I would happily use this book when teaching Physical Design. I know of no other work that's as comprehensive and up-to-date, with algorithmic focus and clear pseudocode for the key algorithms. The book is beautifully designed! Prof. John P. Hayes, University of Michigan ------- The entire field of electronic design automation owes the authors a great debt for providing a single coherent source on physical design that is clear and tutorial in nature, while providing details on key state-of-the-art topics such as timing closure. Prof. Kurt Keutzer, University of California, Berkeley ------- An excellent balance of the basics and more advanced concepts, presented by top experts in the field. Prof. Sachin Sapatnekar, University of Minnesota

• 1 Introduction. 2 Netlist and System Partitioning. 3 Chip Planning. 4 Global and Detailed Placement. 5 Global Routing. 6 Detailed Routing. 7 Specialized Routing. 8 Timing Closure. A Solutions to Chapter Exercises. B Example CMOS Cell Layouts.