Professor Dr. Hafiz Md. Hasan Babu is currently working as a Professor in the Department of Computer Science and Engineering, University of Dhaka, Bangladesh. He is also the former Chairman of the same department. Recently, he has completed his tenured as Pro-Vice-Chancellor of National University, Bangladesh, where he was on deputation from the Department of Computer Science and Engineering, University of Dhaka, Bangladesh. For his excellent academic and administrative capability, he also served as the Professor and founding Chairman of the Department of Robotics and Mechatronics Engineering, University of Dhaka, Bangladesh. He served as a World Bank Senior Consultant and General Manager of the Department of the Information Technology & the Department of Management Information Systems of Janata Bank Limited, Bangladesh. Dr. Hasan Babu was the World Bank Resident Information Technology Expert of the Supreme Court Project Implementation Committee, Supreme Court of Bangladesh. He was also the Information Technology Consultant of Health Economics Unit and the Ministry of Health and Family Welfare in the project "SSK (Shasthyo Shurokhsha Karmasuchi) and Social Health Protection Scheme" under the direct supervision and funding of German Financial Cooperation through KfW.

• Part-1: Decision Diagrams (DDs) Chapter 1: Shared Multi-Terminal Binary Decision DiagramsChapter 2: Multiple-Output Functions Chapter 3: Shared Multiple-Valued DDs for Multiple-Output FunctionsChapter 4: Heuristics to Minimize Multiple-Valued DDsChapter 5: TDM Realizations of Multiple-Output Functions Chapter 6: Multiple-Output Switching FunctionsPart-2: An Overview About Design Architectures of Multiple-Valued CircuitsChapter 7: Multiple-Valued Flip-Flops using Pass Transistor LogicChapter 8: Voltage-Mode Pass Transistor-based Multi-Valued Multiple-Output Logic CircuitsChapter 9: Multiple-Valued Input Binary-Valued Output FunctionsChapter 10: Digital Fuzzy Operations using Multi-Valued Fredkin GatesChapter 11: Multiple-Valued Multiple-Output Logic Expressions using LUTPart-3: Programmable Logic DevicesChapter 12: LUT-Based Matrix Multiplication Using Neural NetworksChapter 13: Easily Testable PLAs using Pass Transistor LogicChapter 14: Genetic Algorithm for Input Assignment for Decoded-PLAsChapter 15: FPGA-based Multiplier using LUT Merging TheoremChapter 16: Look-Up Table-based Binary Coded Decimal AdderChapter 17: Place and Route Algorithm for Field Programmable Gate ArrayChapter 18: LUT-based BCD Multiplier DesignChapter 19: LUT-based Matrix Multiplier Circuit using Pigeonhole PrincipleChapter 20: BCD Adder using a LUT-based Field Programmable Gate ArrayChapter 21: Generic Complex Programmable Logic Device BoardChapter 22: FPGA-based Programmable Logic Controller Part-IV: Design Architectures of Advanced Digital CircuitsChapter 23: Parallel Computation of Quotients and Partial Remainders to Design Divider CircuitsChapter 24: Synthesis of Boolean Functions using TANT NetworksChapter 25: Asymmetric High Radix Signed Digital Adder using Neural NetworksChapter 26: Wrapper/TAM Co-Optimization and Constrained Test Scheduling for SOCs using Rectangle Bin PackingChapter 27: Static Random Access Memory using MemristorChapter 28: A Fault Tolerant Approach to Microprocessor DesignChapter 29: Applications of VLSI Circuits and Embedded Systems

Professor Dr. Hafiz Md. Hasan Babu is currently working as a Professor in the Department of Computer Science and Engineering, University of Dhaka, Bangladesh. He is also the former Chairman of the same department. Recently, he has completed his tenured as Pro-Vice-Chancellor of National University, Bangladesh, where he was on deputation from the Department of Computer Science and Engineering, University of Dhaka, Bangladesh. For his excellent academic and administrative capability, he also served as the Professor and founding Chairman of the Department of Robotics and Mechatronics Engineering, University of Dhaka, Bangladesh. He served as a World Bank Senior Consultant and General Manager of the Department of the Information Technology & the Department of Management Information Systems of Janata Bank Limited, Bangladesh. Dr. Hasan Babu was the World Bank Resident Information Technology Expert of the Supreme Court Project Implementation Committee, Supreme Court of Bangladesh. He was also the Information Technology Consultant of Health Economics Unit and the Ministry of Health and Family Welfare in the project "SSK (Shasthyo Shurokhsha Karmasuchi) and Social Health Protection Scheme" under the direct supervision and funding of German Financial Cooperation through KfW.

• Part-1: Decision Diagrams (DDs) Chapter 1: Shared Multi-Terminal Binary Decision DiagramsChapter 2: Multiple-Output Functions Chapter 3: Shared Multiple-Valued DDs for Multiple-Output FunctionsChapter 4: Heuristics to Minimize Multiple-Valued DDsChapter 5: TDM Realizations of Multiple-Output Functions Chapter 6: Multiple-Output Switching FunctionsPart-2: An Overview About Design Architectures of Multiple-Valued CircuitsChapter 7: Multiple-Valued Flip-Flops using Pass Transistor LogicChapter 8: Voltage-Mode Pass Transistor-based Multi-Valued Multiple-Output Logic CircuitsChapter 9: Multiple-Valued Input Binary-Valued Output FunctionsChapter 10: Digital Fuzzy Operations using Multi-Valued Fredkin GatesChapter 11: Multiple-Valued Multiple-Output Logic Expressions using LUTPart-3: Programmable Logic DevicesChapter 12: LUT-Based Matrix Multiplication Using Neural NetworksChapter 13: Easily Testable PLAs using Pass Transistor LogicChapter 14: Genetic Algorithm for Input Assignment for Decoded-PLAsChapter 15: FPGA-based Multiplier using LUT Merging TheoremChapter 16: Look-Up Table-based Binary Coded Decimal AdderChapter 17: Place and Route Algorithm for Field Programmable Gate ArrayChapter 18: LUT-based BCD Multiplier DesignChapter 19: LUT-based Matrix Multiplier Circuit using Pigeonhole PrincipleChapter 20: BCD Adder using a LUT-based Field Programmable Gate ArrayChapter 21: Generic Complex Programmable Logic Device BoardChapter 22: FPGA-based Programmable Logic Controller Part-IV: Design Architectures of Advanced Digital CircuitsChapter 23: Parallel Computation of Quotients and Partial Remainders to Design Divider CircuitsChapter 24: Synthesis of Boolean Functions using TANT NetworksChapter 25: Asymmetric High Radix Signed Digital Adder using Neural NetworksChapter 26: Wrapper/TAM Co-Optimization and Constrained Test Scheduling for SOCs using Rectangle Bin PackingChapter 27: Static Random Access Memory using MemristorChapter 28: A Fault Tolerant Approach to Microprocessor DesignChapter 29: Applications of VLSI Circuits and Embedded Systems