Shunpei Yamazaki, Semiconductor Energy Laboratory Co., Ltd., Kanagawa, JAPAN Dr. Shunpei Yamazaki is an authority on semiconductors, memory devices, and liquid crystal displays. Listed on over 4,000 US utility patents, Dr. Yamazaki was named in the Guinness Book of World Records as holding the most patents in the world; hailed the most prolific inventor in history by USA Today (in 2005). His most notable work is on the thin-film transistor -- a significant discovery being a crystalline structure in Indium gallium zinc oxide (IGZO) material, which he discovered "by chance" in 2009. Today Dr. Yamazaki is President of the Semiconductor Energy Laboratory (SEL), where he and his team pioneered the unique development of ultra-low-power devices using CAAC-IGZO technology. A joint venture with the Sharp Corporation manufacturing smartphones using crystalline oxide semiconductors (IGZO) is a global first. In 2015 Dr. Yamazaki received the SID (Society for Information Display) Special Recognition Award for "discovering CAAC-IGZO semiconductors, leading its practical application, and paving the way to next-generation displays." His paper on CAAC-IGZO ranked in the top 15 most downloaded papers of Wiley Electrical Engineering and Communications Technology journals, 2014. Dr. Yamazaki is also an IEEE Life Fellow. Masahiro Fujita, University of Tokyo, Japan Masahiro Fujita: received his Ph.D. in Information Engineering from the University of Tokyo in 1985 on his work on model checking of hardware designs by using logic programming languages. In 1985, he joined Fujitsu as a researcher and started to work on hardware automatic synthesis as well as formal verification methods and tools. From 1993 to 2000, he was director at Fujitsu Laboratories of America and headed a hardware formal verification group developing a formal verifier for real-life designs. Since March 2000, he has been a professor at VLSI Design and Education Center of the University of Tokyo. He has authored and co-authored more than 10 books and 300 publications, and has been given several awards from scientific societies. His research interests include synthesis and verification of hardware and software systems.

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• About the Editors xList of Contributors xiiSeries Editor’s Foreword xiiiPreface xvAcknowledgments xviii1 Introduction 11.1 Overview of this Book 11.2 Background 31.2.1 Typical Characteristics of CAAC-IGZO FETs 31.2.2 Possible Applications of CAAC-IGZO FETs 41.3 Summary of Each Chapter 7References 92 Device Physics of CAAC-IGZO FET 112.1 Introduction 112.2 Off-State Current 142.2.1 Off-State Current Comparison between Si and CAAC-IGZO FETs 142.2.2 Measurement of Extremely Low Off-State Current 162.2.3 Theoretical Discussion with Energy Band Diagram 232.2.4 Conclusion 282.3 Subthreshold Characteristics 292.3.1 Estimation of Icut by SS 302.3.2 Extraction Method of Interface Levels 332.3.3 Reproduction of Measured Value and Estimation of Icut 352.3.4 Conclusion 382.4 Technique for Controlling Threshold Voltage (Vth) 392.4.1 Vth Control by Application of Back-Gate Bias 392.4.2 Vth Control by Formation of Circuit for Retaining Back-Gate Bias 422.4.3 Vth Control by Charge Injection into the Charge Trap Layer 452.4.4 Conclusion 492.5 On-State Characteristics 492.5.1 Channel-Length Dependence of Field-Effect Mobility 502.5.2 Measurement of Cut-off Frequency 592.5.3 Summary 622.6 Short-Channel Effect 622.6.1 Features of S-ch CAAC-IGZO FETs 632.6.2 Effect of S-ch Structure 702.6.3 Intrinsic Accumulation-Mode Device 712.6.4 Dielectric Anisotropy 742.6.5 Numerical Calculation of the Band Diagrams in IGZO FETs 762.6.6 Summary 822.7 20-nm-Node CAAC-IGZO FET 832.7.1 TGSA CAAC-IGZO FET 832.7.2 Device Characteristics 862.7.3 Memory-Retention Characteristics 892.7.4 Summary 922.8 Hybrid Structure 922.8.1 TGTC Structure 932.8.2 TGSA Structure 942.8.3 Hybrid Structure 96Appendix: Comparison between CAAC-IGZO and Si 98References 993 NOSRAM 1023.1 Introduction 1023.2 Memory Characteristics 1033.3 Application of CAAC-IGZO FETs to Memory and their Operation 1043.4 Configuration and Operation of NOSRAM Module 1063.4.1 NOSRAM Module 1063.4.2 Setting Operational Voltage of NOSRAM Module 1063.4.3 Operation of NOSRAM Module 1083.5 Multilevel NOSRAM 1083.5.1 4-Level (2 Bits/Cell) NOSRAM Module 1103.5.2 8-Level (3 Bits/Cell) NOSRAM Module 1123.5.3 16-Level (4 Bits/Cell) NOSRAM Module 1143.5.4 Stacked Multilevel NOSRAM 1193.6 Prototype and Characterization 1203.6.1 2-Level NOSRAM 1203.6.2 4-Level NOSRAM 1283.6.3 8-Level NOSRAM 1283.6.4 16-Level NOSRAM 1293.6.5 Comparison of Prototypes 133References 1364 DOSRAM 1374.1 Introduction 1374.2 Characteristics and Problems of DRAM 1384.3 Operations and Characteristics of DOSRAM Memory Cell 1384.4 Configuration and Basic Operation of DOSRAM 1394.4.1 Circuit Configuration and Operation of DOSRAM 1394.4.2 Hybrid Structure of DOSRAM 1394.5 Operation of Sense Amplifier 1404.5.1 Writing Operation 1404.5.2 Reading Operation 1414.6 Characteristic Measurement 1434.6.1 Writing Characteristics 1434.6.2 Reading Characteristics 1444.6.3 Data-Retention Characteristics 1454.6.4 Summary of 8-kbit DOSRAM 1464.7 Prototype DOSRAM Using 60-nm Technology Node 1474.7.1 Configuration of Prototype 1474.7.2 Measurements of Prototype Characteristics 1484.7.3 Summary for Prototype DOSRAM 1514.8 Conclusion 151References 1525 CPU 1535.1 Introduction 1535.2 Normally-Off Computing 1535.3 CPUs 1565.3.1 Flip-Flop (FF) 1585.3.2 8-Bit Normally-Off CPU 1665.3.3 32-Bit Normally-Off CPU (MIPS-Like CPU) 1705.3.4 32-Bit Normally-Off CPU (ARM® Cortex®-M0) 1745.4 CAAC-IGZO Cache Memory 181References 1926 FPGA 1946.1 Introduction 1946.2 CAAC-IGZO FPGA 1956.2.1 Overview 1956.2.2 PRS 1976.2.3 PLE 2006.2.4 Prototype 2026.3 Multicontext FPGA Realizing Fine-Grained Power Gating 2096.3.1 Overview 2096.3.2 Normally-Off Computing 2096.3.3 Prototype 2166.4 Subthreshold Operation of FPGA 2266.4.1 Overview 2266.4.2 Subthreshold Operation 2276.4.3 Prototype 2346.5 CPU + FPGA 2406.5.1 Overview 2406.5.2 CPU Computing 2416.5.3 CPU + GPU Computing 2426.5.4 CPU + FPGA Computing 2436.5.5 CAAC-IGZO CPU + CAAC-IGZO FPGA Computing 246References 2477 Image Sensor 2507.1 Introduction 2507.2 Global Shutter Image Sensor 2517.2.1 Sensor Pixel 2517.2.2 Global and Rolling Shutters 2527.2.3 Challenges Facing Adoption of Global Shutter 2547.2.4 CAAC-IGZO Image Sensor 2557.3 Image Sensor Conducting High-Speed Continuous Image Capture 2627.3.1 Overview 2627.3.2 Conventional High-Speed Continuous-Capturing Image Sensor 2637.3.3 High-Speed Continuous-Capturing CAAC-IGZO Image Sensor 2637.3.4 Application to Optical Flow System 2767.4 Motion Sensor 2787.4.1 Overview 2787.4.2 Configuration 2787.4.3 Prototype 2837.4.4 Sensor Pixel Threshold-Compensation Function 285References 2918 Future Applications/Developments 2938.1 Introduction 2938.2 RF Devices 2948.2.1 Overview 2948.2.2 NOSRAM Wireless IC Tag 2948.2.3 Application Examples of NOSRAM Wireless IC Tags 2988.3 X-Ray Detector 3038.3.1 Outline 3038.3.2 X-Ray Detection Principle 3038.3.3 CAAC-IGZO X-Ray Detector 3048.3.4 Fabrication Example and Evaluation 3088.4 CODEC 3108.4.1 Introduction 3108.4.2 Encoder/Decoder 3118.4.3 CAAC-IGZO CODEC 3138.5 DC–DC Converters 3148.5.1 Introduction 3148.5.2 Non-hybrid DC–DC Converter 3158.5.3 Fabricated CAAC-IGZO Bias Voltage Sampling Circuit with Amplifier 3158.5.4 Evaluation Results of Fabricated CAAC-IGZO Bias Voltage Sampling Circuit with Amplifier 3178.5.5 Proposed DC–DC Converter 3188.6 Analog Programmable Devices 3228.6.1 Overview 3228.6.2 Design 3228.6.3 Prototype 3238.6.4 Possible Application to Phase-Locked Loop 3308.7 Neural Networks 3308.7.1 Introduction 3308.7.2 Neural Networks 3308.7.3 CAAC-IGZO Neural Network 3328.7.4 Conclusion 3348.8 Memory-Based Computing 3358.9 Backtracking Programs with Power Gating 339References 341Appendix 343Index 345