José M. de la Rosa is a Professor at the Institute of Microelectronics of Seville, IMSE-CNM (CSIC, University of Seville, Spain). His main research interests are in the field of analog and mixed-signal integrated circuits, especially high-performance sigma-delta converters. He has worked in a number of international research and industrial projects and has co-authored over 200 peer-reviewed conference and journal papers dealing with sigma-delta ADCs. He served as Associated Editor of the IEEE Transactions on Circuits and Systems – I: Regular Papers, as Deputy Editor in Chief of the IEEE Transactions on Circuits and Systems – II: Express Briefs, and as Distinguished Lecturer of the IEEE Circuits and Systems Society.

• Preface xixAcknowledgements xxvList of Abbreviations xxvii1 Introduction to ;;;; Modulators: Fundamentals, Basic Architecture and Performance Metrics 11.1 Basics of Analog-to-Digital Conversion 21.2 Sigma-Delta Modulation 91.3 The First-order ΣΔ Modulator 131.4 Performance Enhancement and Taxonomy of ΣΔMs 161.5 Putting All The Pieces Together: From ΣΔMs to ΣΔ ADCs 191.6 ΣΔ DACs 221.7 Summary 25References 262 Taxonomy of ;;;; Architectures 292.1 Second-order ΣΔ Modulators 302.2 High-order Single-loop ΣΔMs 352.3 Cascade ΣΔ Modulators 392.4 Multi-bit ΣΔ Modulators 492.5 Band-pass ΣΔ Modulators 552.6 Continuous-time ΣΔ Modulators: Architecture and Basic Concepts 642.7 DT–CT Transformation of ΣΔMs 702.8 Direct Synthesis of CT-ΣΔMs 742.9 Summary 76References 763 Circuit Errors in Switched-capacitor ;;;; Modulators 833.1 Overview of Nonidealities in Switched-capacitor ΣΔ Modulators 843.2 Finite Amplifier Gain in SC-ΣΔMs 863.3 Capacitor Mismatch in SC-ΣΔMs 903.4 Integrator Settling Error in SC-ΣΔMs 913.5 Circuit Noise in SC-ΣΔMs 1013.6 Clock Jitter in SC-ΣΔMs 1053.7 Sources of Distortion in SC-ΣΔMs 1073.8 Case Study: High-level Sizing of a ΣΔM 1113.9 Summary 119References 1194 Circuit Errors and Compensation Techniques in Continuous-time ;;;; Modulators 1234.1 Overview of Nonidealities in Continuous-time ΣΔ Modulators 1234.2 CT Integrators and Resonators 1244.3 Finite Amplifier Gain in CT-ΣΔMs 1264.4 Time-constant Error in CT-ΣΔMs 1284.5 Finite Integrator Dynamics in CT-ΣΔMs 1304.6 Sources of Distortion in CT-ΣΔMs 1344.7 Circuit Noise in CT-ΣΔMs 1374.8 Clock Jitter in CT-ΣΔMs 1404.9 Excess Loop Delay in CT-ΣΔMs 1494.10 Quantizer Metastability in CT-ΣΔMs 1554.11 Summary 159References 1605 Behavioral Modeling and High-level Simulation 1655.1 Systematic Design Methodology of ΣΔ Modulators 1655.2 Simulation Approaches for the High-level Evaluation of ΣΔMs 1695.3 Implementing ΣΔM Behavioral Models 1735.4 Efficient Behavioral Modeling of ΣΔM Building Blocks using C-MEX S-functions 1885.5 SIMSIDES: A SIMULINK-based Behavioral Simulator for ΣΔMs 2095.6 Using SIMSIDES for High-level Sizing and Verification of ΣΔMs 2165.7 Summary 231References 2316 Automated Design and Optimization of ;;;;Ms 2356.1 Architecture Exploration and Selection: Schreier’s Toolbox 2366.2 Optimization-based High-level Synthesis of ΣΔ Modulators 2456.3 Lifting Method and Hardware Acceleration to Optimize CT-ΣΔMs 2556.4 Using Multi-objective Evolutionary Algorithms to Optimize ΣΔMs 2596.5 Summary 269References 2697 Electrical Design of ;;;;Ms: From Systems to Circuits 2717.1 Macromodeling ΣΔMs 2727.2 Examples of ΣΔM Macromodels 2797.3 Including Noise in Transient Electrical Simulations of ΣΔMs 2867.4 Processing ΣΔM Output Results of Electrical Simulations 2947.5 Summary 298References 2988 Design Considerations of ;;;;M Subcircuits 3018.1 Design Considerations of CMOS Switches 3028.2 Design Considerations of Operational Amplifiers 3088.3 Design Considerations of Transconductors 3178.4 Design Considerations of Comparators 3248.5 Design Considerations of Current-Steering DACs 3328.6 Summary 338References 3389 Practical Realization of ;;;;Ms: From Circuits to Chips 3419.1 Auxiliary ΣΔM Building Blocks 3419.2 Layout Design, Floorplanning, and Practical Issues 3489.3 Chip Package, Test PCB, and Experimental Setup 3549.4 Experimental Test Set-Up 3559.5 ΣΔM Design Examples and Case Studies 3599.6 Summary 385References 38610 Frontiers, Trends and Challenges: Towards Next-generation ;;;; Modulators 38910.1 State-of-the-Art ADCs: Nyquist-rate versus ΣΔ Converters 39010.2 Comparison of Different Categories of ΣΔ ADCs 39310.3 Empirical and Statistical Analysis of State-of-the-Art ΣΔMs 40810.4 Gigahertz-range ΣΔMs for RF-to-digital Conversion 41510.5 Enhanced Cascade ΣΔMs 41810.6 Power-efficient ΣΔM Loop-filter Techniques 42310.7 Hybrid ΣΔM/Nyquist-rate ADCs 42810.8 Time-based ΣΔ ADCs 43110.9 DAC Techniques for High-performance CT-ΣΔMs 43610.10 Classification of State-of-the-Art References 43710.11 Summary and Conclusions 437References 438A State-space Analysis of Clock Jitter in CT-;;;;Ms 463A.1 State-space Representation of NTF (z) 463A.2 Expectation Value of (Δqn)2 465A.3 In-band Noise Power due to Clock Jitter 466References 467B SIMSIDES User Guide 469B.1 Getting Started: Installing and Running SIMSIDES 470B.2 Building and Editing ΣΔM Architectures in SIMSIDES 470B.3 Analyzing ΣΔMs in SIMSIDES 473B.3.1 Node Spectrum Analysis 474B.3.2 Integrated Power Noise 474B.3.3 SNR/SNDR 475B.3.4 Harmonic Distortion 475B.3.5 Integral and Differential Non-Linearity 477B.3.6 Multi-tone Power Ratio 477B.3.7 Histogram 478B.3.8 Parametric Analysis 478B.3.9 Monte Carlo Analysis 479B.4 Optimization Interface 480B.5 Tutorial Example: Using SIMSIDES to Model and Analyze ΣΔMs 482B.5.1 Creating the Cascade 2-1 ΣΔM Block Diagram in SIMSIDES 482B.5.2 Setting Model Parameters 482B.5.3 Computing the Output Spectrum 484B.5.4 SNR versus Input Amplitude Level 486B.5.5 Parametric Analysis Considering Only One Parameter 487B.5.6 Parametric Analysis Considering Two Parameters 488B.5.7 Computing Histograms 489B.6 Getting Help 489C SIMSIDES Block Libraries and Models 491C.1 Overview of SIMSIDES Libraries 491C.2 Ideal Libraries 492C.2.1 Ideal Integrators 492C.2.1.1 Building-block Model Purpose and Description 492C.2.1.2 Model Parameters 493C.2.2 Ideal Resonators 493C.2.2.1 Ideal_LD_Resonator 493C.2.2.2 Ideal_FE_Resonator 493C.2.2.3 Ideal_CT_Resonator 493C.2.3 Ideal Quantizers 494C.2.3.1 Ideal_Comparator 494C.2.3.2 Ideal_Comparator_for_SI 495C.2.3.3 Ideal_Multibit_Quantizer 495C.2.3.4 Ideal_Multibit_Quantizer_for_SI 496C.2.3.5 Ideal_Multibit_Quantizer_levels 496C.2.3.6 Ideal_Multibit_Quantizer_levels_SD2 496C.2.3.7 Ideal_Sampler 496C.2.4 Ideal D/A Converters 496C.2.4.1 Ideal_DAC_for_SI 496C.2.4.2 Ideal_DAC_dig_level_SD2 497C.3 Real SC Building-Block Libraries 497C.3.1 Real SC Integrators 497C.3.2 Real SC Resonators 501C.4 Real SI Building-Block Libraries 503C.4.1 Real SI Integrators 503C.4.2 Real SI Resonators 505C.4.3 SI Errors and Model Parameters 506C.4.3.1 Basic_SI_FE(LD)_Integrator and Basic_SI_FE(LD)_Resonator 506C.4.3.2 SI_FE(LD)_Int_Finite_Conductance 507C.4.3.3 SI_FE(LD)_Int_Finite_Conductance & Settling & ChargeInjection 508C.5 Real CT Building-Block Libraries 508C.5.1 Real CT Integrators 508C.5.1.1 Model Parameters used in Transconductors and Gm-C Integrator Building Blocks 511C.5.1.2 Gm-MC Integrators 511C.5.1.3 Active-RC Integrators 512C.5.1.4 MOSFET-C Integrators 513C.5.2 Real CT Resonators 513C.5.2.1 Gm-C Resonators 514C.5.2.2 Gm-LC Resonators 517C.6 Real Quantizers & Comparators 517C.7 Real D/A Converters 518C.8 Auxiliary Blocks 519Index 523

José M. de la Rosa is a Professor at the Institute of Microelectronics of Seville, IMSE-CNM (CSIC, University of Seville, Spain). His main research interests are in the field of analog and mixed-signal integrated circuits, especially high-performance sigma-delta converters. He has worked in a number of international research and industrial projects and has co-authored over 200 peer-reviewed conference and journal papers dealing with sigma-delta ADCs. He served as Associated Editor of the IEEE Transactions on Circuits and Systems – I: Regular Papers, as Deputy Editor in Chief of the IEEE Transactions on Circuits and Systems – II: Express Briefs, and as Distinguished Lecturer of the IEEE Circuits and Systems Society.

• Preface xixAcknowledgements xxvList of Abbreviations xxvii1 Introduction to ;;;; Modulators: Fundamentals, Basic Architecture and Performance Metrics 11.1 Basics of Analog-to-Digital Conversion 21.2 Sigma-Delta Modulation 91.3 The First-order ΣΔ Modulator 131.4 Performance Enhancement and Taxonomy of ΣΔMs 161.5 Putting All The Pieces Together: From ΣΔMs to ΣΔ ADCs 191.6 ΣΔ DACs 221.7 Summary 25References 262 Taxonomy of ;;;; Architectures 292.1 Second-order ΣΔ Modulators 302.2 High-order Single-loop ΣΔMs 352.3 Cascade ΣΔ Modulators 392.4 Multi-bit ΣΔ Modulators 492.5 Band-pass ΣΔ Modulators 552.6 Continuous-time ΣΔ Modulators: Architecture and Basic Concepts 642.7 DT–CT Transformation of ΣΔMs 702.8 Direct Synthesis of CT-ΣΔMs 742.9 Summary 76References 763 Circuit Errors in Switched-capacitor ;;;; Modulators 833.1 Overview of Nonidealities in Switched-capacitor ΣΔ Modulators 843.2 Finite Amplifier Gain in SC-ΣΔMs 863.3 Capacitor Mismatch in SC-ΣΔMs 903.4 Integrator Settling Error in SC-ΣΔMs 913.5 Circuit Noise in SC-ΣΔMs 1013.6 Clock Jitter in SC-ΣΔMs 1053.7 Sources of Distortion in SC-ΣΔMs 1073.8 Case Study: High-level Sizing of a ΣΔM 1113.9 Summary 119References 1194 Circuit Errors and Compensation Techniques in Continuous-time ;;;; Modulators 1234.1 Overview of Nonidealities in Continuous-time ΣΔ Modulators 1234.2 CT Integrators and Resonators 1244.3 Finite Amplifier Gain in CT-ΣΔMs 1264.4 Time-constant Error in CT-ΣΔMs 1284.5 Finite Integrator Dynamics in CT-ΣΔMs 1304.6 Sources of Distortion in CT-ΣΔMs 1344.7 Circuit Noise in CT-ΣΔMs 1374.8 Clock Jitter in CT-ΣΔMs 1404.9 Excess Loop Delay in CT-ΣΔMs 1494.10 Quantizer Metastability in CT-ΣΔMs 1554.11 Summary 159References 1605 Behavioral Modeling and High-level Simulation 1655.1 Systematic Design Methodology of ΣΔ Modulators 1655.2 Simulation Approaches for the High-level Evaluation of ΣΔMs 1695.3 Implementing ΣΔM Behavioral Models 1735.4 Efficient Behavioral Modeling of ΣΔM Building Blocks using C-MEX S-functions 1885.5 SIMSIDES: A SIMULINK-based Behavioral Simulator for ΣΔMs 2095.6 Using SIMSIDES for High-level Sizing and Verification of ΣΔMs 2165.7 Summary 231References 2316 Automated Design and Optimization of ;;;;Ms 2356.1 Architecture Exploration and Selection: Schreier’s Toolbox 2366.2 Optimization-based High-level Synthesis of ΣΔ Modulators 2456.3 Lifting Method and Hardware Acceleration to Optimize CT-ΣΔMs 2556.4 Using Multi-objective Evolutionary Algorithms to Optimize ΣΔMs 2596.5 Summary 269References 2697 Electrical Design of ;;;;Ms: From Systems to Circuits 2717.1 Macromodeling ΣΔMs 2727.2 Examples of ΣΔM Macromodels 2797.3 Including Noise in Transient Electrical Simulations of ΣΔMs 2867.4 Processing ΣΔM Output Results of Electrical Simulations 2947.5 Summary 298References 2988 Design Considerations of ;;;;M Subcircuits 3018.1 Design Considerations of CMOS Switches 3028.2 Design Considerations of Operational Amplifiers 3088.3 Design Considerations of Transconductors 3178.4 Design Considerations of Comparators 3248.5 Design Considerations of Current-Steering DACs 3328.6 Summary 338References 3389 Practical Realization of ;;;;Ms: From Circuits to Chips 3419.1 Auxiliary ΣΔM Building Blocks 3419.2 Layout Design, Floorplanning, and Practical Issues 3489.3 Chip Package, Test PCB, and Experimental Setup 3549.4 Experimental Test Set-Up 3559.5 ΣΔM Design Examples and Case Studies 3599.6 Summary 385References 38610 Frontiers, Trends and Challenges: Towards Next-generation ;;;; Modulators 38910.1 State-of-the-Art ADCs: Nyquist-rate versus ΣΔ Converters 39010.2 Comparison of Different Categories of ΣΔ ADCs 39310.3 Empirical and Statistical Analysis of State-of-the-Art ΣΔMs 40810.4 Gigahertz-range ΣΔMs for RF-to-digital Conversion 41510.5 Enhanced Cascade ΣΔMs 41810.6 Power-efficient ΣΔM Loop-filter Techniques 42310.7 Hybrid ΣΔM/Nyquist-rate ADCs 42810.8 Time-based ΣΔ ADCs 43110.9 DAC Techniques for High-performance CT-ΣΔMs 43610.10 Classification of State-of-the-Art References 43710.11 Summary and Conclusions 437References 438A State-space Analysis of Clock Jitter in CT-;;;;Ms 463A.1 State-space Representation of NTF (z) 463A.2 Expectation Value of (Δqn)2 465A.3 In-band Noise Power due to Clock Jitter 466References 467B SIMSIDES User Guide 469B.1 Getting Started: Installing and Running SIMSIDES 470B.2 Building and Editing ΣΔM Architectures in SIMSIDES 470B.3 Analyzing ΣΔMs in SIMSIDES 473B.3.1 Node Spectrum Analysis 474B.3.2 Integrated Power Noise 474B.3.3 SNR/SNDR 475B.3.4 Harmonic Distortion 475B.3.5 Integral and Differential Non-Linearity 477B.3.6 Multi-tone Power Ratio 477B.3.7 Histogram 478B.3.8 Parametric Analysis 478B.3.9 Monte Carlo Analysis 479B.4 Optimization Interface 480B.5 Tutorial Example: Using SIMSIDES to Model and Analyze ΣΔMs 482B.5.1 Creating the Cascade 2-1 ΣΔM Block Diagram in SIMSIDES 482B.5.2 Setting Model Parameters 482B.5.3 Computing the Output Spectrum 484B.5.4 SNR versus Input Amplitude Level 486B.5.5 Parametric Analysis Considering Only One Parameter 487B.5.6 Parametric Analysis Considering Two Parameters 488B.5.7 Computing Histograms 489B.6 Getting Help 489C SIMSIDES Block Libraries and Models 491C.1 Overview of SIMSIDES Libraries 491C.2 Ideal Libraries 492C.2.1 Ideal Integrators 492C.2.1.1 Building-block Model Purpose and Description 492C.2.1.2 Model Parameters 493C.2.2 Ideal Resonators 493C.2.2.1 Ideal_LD_Resonator 493C.2.2.2 Ideal_FE_Resonator 493C.2.2.3 Ideal_CT_Resonator 493C.2.3 Ideal Quantizers 494C.2.3.1 Ideal_Comparator 494C.2.3.2 Ideal_Comparator_for_SI 495C.2.3.3 Ideal_Multibit_Quantizer 495C.2.3.4 Ideal_Multibit_Quantizer_for_SI 496C.2.3.5 Ideal_Multibit_Quantizer_levels 496C.2.3.6 Ideal_Multibit_Quantizer_levels_SD2 496C.2.3.7 Ideal_Sampler 496C.2.4 Ideal D/A Converters 496C.2.4.1 Ideal_DAC_for_SI 496C.2.4.2 Ideal_DAC_dig_level_SD2 497C.3 Real SC Building-Block Libraries 497C.3.1 Real SC Integrators 497C.3.2 Real SC Resonators 501C.4 Real SI Building-Block Libraries 503C.4.1 Real SI Integrators 503C.4.2 Real SI Resonators 505C.4.3 SI Errors and Model Parameters 506C.4.3.1 Basic_SI_FE(LD)_Integrator and Basic_SI_FE(LD)_Resonator 506C.4.3.2 SI_FE(LD)_Int_Finite_Conductance 507C.4.3.3 SI_FE(LD)_Int_Finite_Conductance & Settling & ChargeInjection 508C.5 Real CT Building-Block Libraries 508C.5.1 Real CT Integrators 508C.5.1.1 Model Parameters used in Transconductors and Gm-C Integrator Building Blocks 511C.5.1.2 Gm-MC Integrators 511C.5.1.3 Active-RC Integrators 512C.5.1.4 MOSFET-C Integrators 513C.5.2 Real CT Resonators 513C.5.2.1 Gm-C Resonators 514C.5.2.2 Gm-LC Resonators 517C.6 Real Quantizers & Comparators 517C.7 Real D/A Converters 518C.8 Auxiliary Blocks 519Index 523

José M. de la Rosa is a Professor at the Institute of Microelectronics of Seville, IMSE-CNM (CSIC, University of Seville, Spain). His main research interests are in the field of analog and mixed-signal integrated circuits, especially high-performance sigma-delta converters. He has worked in a number of international research and industrial projects and has co-authored over 200 peer-reviewed conference and journal papers dealing with sigma-delta ADCs. He served as Associated Editor of the IEEE Transactions on Circuits and Systems – I: Regular Papers, as Deputy Editor in Chief of the IEEE Transactions on Circuits and Systems – II: Express Briefs, and as Distinguished Lecturer of the IEEE Circuits and Systems Society.

• Preface xixAcknowledgements xxvList of Abbreviations xxvii1 Introduction to ;;;; Modulators: Fundamentals, Basic Architecture and Performance Metrics 11.1 Basics of Analog-to-Digital Conversion 21.2 Sigma-Delta Modulation 91.3 The First-order ΣΔ Modulator 131.4 Performance Enhancement and Taxonomy of ΣΔMs 161.5 Putting All The Pieces Together: From ΣΔMs to ΣΔ ADCs 191.6 ΣΔ DACs 221.7 Summary 25References 262 Taxonomy of ;;;; Architectures 292.1 Second-order ΣΔ Modulators 302.2 High-order Single-loop ΣΔMs 352.3 Cascade ΣΔ Modulators 392.4 Multi-bit ΣΔ Modulators 492.5 Band-pass ΣΔ Modulators 552.6 Continuous-time ΣΔ Modulators: Architecture and Basic Concepts 642.7 DT–CT Transformation of ΣΔMs 702.8 Direct Synthesis of CT-ΣΔMs 742.9 Summary 76References 763 Circuit Errors in Switched-capacitor ;;;; Modulators 833.1 Overview of Nonidealities in Switched-capacitor ΣΔ Modulators 843.2 Finite Amplifier Gain in SC-ΣΔMs 863.3 Capacitor Mismatch in SC-ΣΔMs 903.4 Integrator Settling Error in SC-ΣΔMs 913.5 Circuit Noise in SC-ΣΔMs 1013.6 Clock Jitter in SC-ΣΔMs 1053.7 Sources of Distortion in SC-ΣΔMs 1073.8 Case Study: High-level Sizing of a ΣΔM 1113.9 Summary 119References 1194 Circuit Errors and Compensation Techniques in Continuous-time ;;;; Modulators 1234.1 Overview of Nonidealities in Continuous-time ΣΔ Modulators 1234.2 CT Integrators and Resonators 1244.3 Finite Amplifier Gain in CT-ΣΔMs 1264.4 Time-constant Error in CT-ΣΔMs 1284.5 Finite Integrator Dynamics in CT-ΣΔMs 1304.6 Sources of Distortion in CT-ΣΔMs 1344.7 Circuit Noise in CT-ΣΔMs 1374.8 Clock Jitter in CT-ΣΔMs 1404.9 Excess Loop Delay in CT-ΣΔMs 1494.10 Quantizer Metastability in CT-ΣΔMs 1554.11 Summary 159References 1605 Behavioral Modeling and High-level Simulation 1655.1 Systematic Design Methodology of ΣΔ Modulators 1655.2 Simulation Approaches for the High-level Evaluation of ΣΔMs 1695.3 Implementing ΣΔM Behavioral Models 1735.4 Efficient Behavioral Modeling of ΣΔM Building Blocks using C-MEX S-functions 1885.5 SIMSIDES: A SIMULINK-based Behavioral Simulator for ΣΔMs 2095.6 Using SIMSIDES for High-level Sizing and Verification of ΣΔMs 2165.7 Summary 231References 2316 Automated Design and Optimization of ;;;;Ms 2356.1 Architecture Exploration and Selection: Schreier’s Toolbox 2366.2 Optimization-based High-level Synthesis of ΣΔ Modulators 2456.3 Lifting Method and Hardware Acceleration to Optimize CT-ΣΔMs 2556.4 Using Multi-objective Evolutionary Algorithms to Optimize ΣΔMs 2596.5 Summary 269References 2697 Electrical Design of ;;;;Ms: From Systems to Circuits 2717.1 Macromodeling ΣΔMs 2727.2 Examples of ΣΔM Macromodels 2797.3 Including Noise in Transient Electrical Simulations of ΣΔMs 2867.4 Processing ΣΔM Output Results of Electrical Simulations 2947.5 Summary 298References 2988 Design Considerations of ;;;;M Subcircuits 3018.1 Design Considerations of CMOS Switches 3028.2 Design Considerations of Operational Amplifiers 3088.3 Design Considerations of Transconductors 3178.4 Design Considerations of Comparators 3248.5 Design Considerations of Current-Steering DACs 3328.6 Summary 338References 3389 Practical Realization of ;;;;Ms: From Circuits to Chips 3419.1 Auxiliary ΣΔM Building Blocks 3419.2 Layout Design, Floorplanning, and Practical Issues 3489.3 Chip Package, Test PCB, and Experimental Setup 3549.4 Experimental Test Set-Up 3559.5 ΣΔM Design Examples and Case Studies 3599.6 Summary 385References 38610 Frontiers, Trends and Challenges: Towards Next-generation ;;;; Modulators 38910.1 State-of-the-Art ADCs: Nyquist-rate versus ΣΔ Converters 39010.2 Comparison of Different Categories of ΣΔ ADCs 39310.3 Empirical and Statistical Analysis of State-of-the-Art ΣΔMs 40810.4 Gigahertz-range ΣΔMs for RF-to-digital Conversion 41510.5 Enhanced Cascade ΣΔMs 41810.6 Power-efficient ΣΔM Loop-filter Techniques 42310.7 Hybrid ΣΔM/Nyquist-rate ADCs 42810.8 Time-based ΣΔ ADCs 43110.9 DAC Techniques for High-performance CT-ΣΔMs 43610.10 Classification of State-of-the-Art References 43710.11 Summary and Conclusions 437References 438A State-space Analysis of Clock Jitter in CT-;;;;Ms 463A.1 State-space Representation of NTF (z) 463A.2 Expectation Value of (Δqn)2 465A.3 In-band Noise Power due to Clock Jitter 466References 467B SIMSIDES User Guide 469B.1 Getting Started: Installing and Running SIMSIDES 470B.2 Building and Editing ΣΔM Architectures in SIMSIDES 470B.3 Analyzing ΣΔMs in SIMSIDES 473B.3.1 Node Spectrum Analysis 474B.3.2 Integrated Power Noise 474B.3.3 SNR/SNDR 475B.3.4 Harmonic Distortion 475B.3.5 Integral and Differential Non-Linearity 477B.3.6 Multi-tone Power Ratio 477B.3.7 Histogram 478B.3.8 Parametric Analysis 478B.3.9 Monte Carlo Analysis 479B.4 Optimization Interface 480B.5 Tutorial Example: Using SIMSIDES to Model and Analyze ΣΔMs 482B.5.1 Creating the Cascade 2-1 ΣΔM Block Diagram in SIMSIDES 482B.5.2 Setting Model Parameters 482B.5.3 Computing the Output Spectrum 484B.5.4 SNR versus Input Amplitude Level 486B.5.5 Parametric Analysis Considering Only One Parameter 487B.5.6 Parametric Analysis Considering Two Parameters 488B.5.7 Computing Histograms 489B.6 Getting Help 489C SIMSIDES Block Libraries and Models 491C.1 Overview of SIMSIDES Libraries 491C.2 Ideal Libraries 492C.2.1 Ideal Integrators 492C.2.1.1 Building-block Model Purpose and Description 492C.2.1.2 Model Parameters 493C.2.2 Ideal Resonators 493C.2.2.1 Ideal_LD_Resonator 493C.2.2.2 Ideal_FE_Resonator 493C.2.2.3 Ideal_CT_Resonator 493C.2.3 Ideal Quantizers 494C.2.3.1 Ideal_Comparator 494C.2.3.2 Ideal_Comparator_for_SI 495C.2.3.3 Ideal_Multibit_Quantizer 495C.2.3.4 Ideal_Multibit_Quantizer_for_SI 496C.2.3.5 Ideal_Multibit_Quantizer_levels 496C.2.3.6 Ideal_Multibit_Quantizer_levels_SD2 496C.2.3.7 Ideal_Sampler 496C.2.4 Ideal D/A Converters 496C.2.4.1 Ideal_DAC_for_SI 496C.2.4.2 Ideal_DAC_dig_level_SD2 497C.3 Real SC Building-Block Libraries 497C.3.1 Real SC Integrators 497C.3.2 Real SC Resonators 501C.4 Real SI Building-Block Libraries 503C.4.1 Real SI Integrators 503C.4.2 Real SI Resonators 505C.4.3 SI Errors and Model Parameters 506C.4.3.1 Basic_SI_FE(LD)_Integrator and Basic_SI_FE(LD)_Resonator 506C.4.3.2 SI_FE(LD)_Int_Finite_Conductance 507C.4.3.3 SI_FE(LD)_Int_Finite_Conductance & Settling & ChargeInjection 508C.5 Real CT Building-Block Libraries 508C.5.1 Real CT Integrators 508C.5.1.1 Model Parameters used in Transconductors and Gm-C Integrator Building Blocks 511C.5.1.2 Gm-MC Integrators 511C.5.1.3 Active-RC Integrators 512C.5.1.4 MOSFET-C Integrators 513C.5.2 Real CT Resonators 513C.5.2.1 Gm-C Resonators 514C.5.2.2 Gm-LC Resonators 517C.6 Real Quantizers & Comparators 517C.7 Real D/A Converters 518C.8 Auxiliary Blocks 519Index 523