Woogeun Rhee, PhD, is a Professor at the School of Integrated Circuits, Tsinghua University, Beijing. He has over 25 years of professional career experience in integrated circuit design with nearly 10 years in industry and 16 years in academia. Dr. Rhee is one of a few researchers who made significant contributions to PLL architectures and circuits not only within different careers (academia and industry) but also over different fields (wireless and wireline systems). He is an IEEE Fellow. Zhiping Yu, PhD, is a Professor at the School of Integrated Circuits, Tsinghua University, Beijing. He is an IEEE Life Fellow with over 400 published papers on subjects related to ICCAD, nanoelectronics and RF circuit design.

• Preface xiiiAbout Authors xv1 Introduction 11.1 Phase-Lock Technique 11.2 Key Properties and Applications 21.3 Organization and Scope of the Book 6Part I Phase-Lock Basics 92 Linear Model and Loop Dynamics 112.1 Linear Model of the PLL 112.2 Feedback System 132.3 Loop Dynamics of the PLL 162.4 Noise Transfer Function 262.5 Charge-Pump PLL 292.6 Other Design Considerations 393 Transient Response 433.1 Linear Transient Performance 443.2 Nonlinear Transient Performance 523.3 Practical Design Aspects 56Part II System Perspectives 674 Frequency and Spectral Purity 694.1 Spur Generation and Modulation 694.2 Phase Noise and Random Jitter 875 Application Aspects 1015.1 Frequency Synthesis 1025.2 Clock-and-Data Recovery 1125.3 Clock Generation 1205.4 Synchronization 127Part III Building Circuits 1356 PhaseDetector 1376.1 Non-Memory Phase Detectors 1376.2 Phase-Frequency Detector 1426.3 Charge Pump 1497 Voltage-Controlled Oscillator 1657.1 Oscillator Basics 1667.2 LC VCO 1757.3 RING VCO 1907.4 Relaxation VCO 2018 FrequencyDivider 2098.1 Basic Operation 2098.2 Circuit Design Considerations 2198.3 Other Topologies 229Part IV PLL Architectures 2379 Fractional-N PLL 2399.1 Fractional-N Frequency Synthesis 2399.2 Frequency Synthesis with Delta-Sigma Modulation 2499.3 Quantization Noise Reduction Methods 2719.4 Frequency Modulation by Fractional-N PLL 27810 Digital-Intensive PLL 28710.1 DPLL with Linear TDC 28810.2 DPLL with 1-Bit TDC 30410.3 Hybrid PLL 31511 Clock-and-Data Recovery PLL 32511.1 Loop Dynamics Considerations for CDR 32511.2 CDR PLL Architectures Based on Phase Detection 32911.3 Frequency Acquisition 34011.4 DLL-assisted CDR Architectures 34411.5 Open-Loop CDR Architectures 351References 355Index 359

Woogeun Rhee, PhD, is a Professor at the School of Integrated Circuits, Tsinghua University, Beijing. He has over 25 years of professional career experience in integrated circuit design with nearly 10 years in industry and 16 years in academia. Dr. Rhee is one of a few researchers who made significant contributions to PLL architectures and circuits not only within different careers (academia and industry) but also over different fields (wireless and wireline systems). He is an IEEE Fellow. Zhiping Yu, PhD, is a Professor at the School of Integrated Circuits, Tsinghua University, Beijing. He is an IEEE Life Fellow with over 400 published papers on subjects related to ICCAD, nanoelectronics and RF circuit design.

• Preface xiiiAbout Authors xv1 Introduction 11.1 Phase-Lock Technique 11.2 Key Properties and Applications 21.3 Organization and Scope of the Book 6Part I Phase-Lock Basics 92 Linear Model and Loop Dynamics 112.1 Linear Model of the PLL 112.2 Feedback System 132.3 Loop Dynamics of the PLL 162.4 Noise Transfer Function 262.5 Charge-Pump PLL 292.6 Other Design Considerations 393 Transient Response 433.1 Linear Transient Performance 443.2 Nonlinear Transient Performance 523.3 Practical Design Aspects 56Part II System Perspectives 674 Frequency and Spectral Purity 694.1 Spur Generation and Modulation 694.2 Phase Noise and Random Jitter 875 Application Aspects 1015.1 Frequency Synthesis 1025.2 Clock-and-Data Recovery 1125.3 Clock Generation 1205.4 Synchronization 127Part III Building Circuits 1356 PhaseDetector 1376.1 Non-Memory Phase Detectors 1376.2 Phase-Frequency Detector 1426.3 Charge Pump 1497 Voltage-Controlled Oscillator 1657.1 Oscillator Basics 1667.2 LC VCO 1757.3 RING VCO 1907.4 Relaxation VCO 2018 FrequencyDivider 2098.1 Basic Operation 2098.2 Circuit Design Considerations 2198.3 Other Topologies 229Part IV PLL Architectures 2379 Fractional-N PLL 2399.1 Fractional-N Frequency Synthesis 2399.2 Frequency Synthesis with Delta-Sigma Modulation 2499.3 Quantization Noise Reduction Methods 2719.4 Frequency Modulation by Fractional-N PLL 27810 Digital-Intensive PLL 28710.1 DPLL with Linear TDC 28810.2 DPLL with 1-Bit TDC 30410.3 Hybrid PLL 31511 Clock-and-Data Recovery PLL 32511.1 Loop Dynamics Considerations for CDR 32511.2 CDR PLL Architectures Based on Phase Detection 32911.3 Frequency Acquisition 34011.4 DLL-assisted CDR Architectures 34411.5 Open-Loop CDR Architectures 351References 355Index 359

Woogeun Rhee, PhD, is a Professor at the School of Integrated Circuits, Tsinghua University, Beijing. He has over 25 years of professional career experience in integrated circuit design with nearly 10 years in industry and 16 years in academia. Dr. Rhee is one of a few researchers who made significant contributions to PLL architectures and circuits not only within different careers (academia and industry) but also over different fields (wireless and wireline systems). He is an IEEE Fellow. Zhiping Yu, PhD, is a Professor at the School of Integrated Circuits, Tsinghua University, Beijing. He is an IEEE Life Fellow with over 400 published papers on subjects related to ICCAD, nanoelectronics and RF circuit design.

• Preface xiiiAbout Authors xv1 Introduction 11.1 Phase-Lock Technique 11.2 Key Properties and Applications 21.3 Organization and Scope of the Book 6Part I Phase-Lock Basics 92 Linear Model and Loop Dynamics 112.1 Linear Model of the PLL 112.2 Feedback System 132.3 Loop Dynamics of the PLL 162.4 Noise Transfer Function 262.5 Charge-Pump PLL 292.6 Other Design Considerations 393 Transient Response 433.1 Linear Transient Performance 443.2 Nonlinear Transient Performance 523.3 Practical Design Aspects 56Part II System Perspectives 674 Frequency and Spectral Purity 694.1 Spur Generation and Modulation 694.2 Phase Noise and Random Jitter 875 Application Aspects 1015.1 Frequency Synthesis 1025.2 Clock-and-Data Recovery 1125.3 Clock Generation 1205.4 Synchronization 127Part III Building Circuits 1356 PhaseDetector 1376.1 Non-Memory Phase Detectors 1376.2 Phase-Frequency Detector 1426.3 Charge Pump 1497 Voltage-Controlled Oscillator 1657.1 Oscillator Basics 1667.2 LC VCO 1757.3 RING VCO 1907.4 Relaxation VCO 2018 FrequencyDivider 2098.1 Basic Operation 2098.2 Circuit Design Considerations 2198.3 Other Topologies 229Part IV PLL Architectures 2379 Fractional-N PLL 2399.1 Fractional-N Frequency Synthesis 2399.2 Frequency Synthesis with Delta-Sigma Modulation 2499.3 Quantization Noise Reduction Methods 2719.4 Frequency Modulation by Fractional-N PLL 27810 Digital-Intensive PLL 28710.1 DPLL with Linear TDC 28810.2 DPLL with 1-Bit TDC 30410.3 Hybrid PLL 31511 Clock-and-Data Recovery PLL 32511.1 Loop Dynamics Considerations for CDR 32511.2 CDR PLL Architectures Based on Phase Detection 32911.3 Frequency Acquisition 34011.4 DLL-assisted CDR Architectures 34411.5 Open-Loop CDR Architectures 351References 355Index 359