VLSI Architectures for Modern Error-Correcting Codes

Xinmiao Zhang received her Ph.D in electrical engineering from the University of Minnesota, Twin Cities, USA. She is currently an Associate Professor in the Department of Electrical and Computer Engineering at The Ohio State University. Previously, she was a Timothy E. and Allison L. Schroeder Associate Professor at Case Western Reserve University, Cleveland, Ohio. Between her academic positions, she continued her research on error-correcting codes at SanDisk/Western Digital Corporation. She has also been a visiting professor at Qualcomm and spent her sabbatical leave at the University of Washington, Seattle, USA. Her research focuses on VLSI architecture design for communications, digital signal processing, and cryptography. She is a recipient of the National Science Foundation Faculty Early Career Development (CAREER) Award.

"Error-correction coding has become an ineluctable feature for the development of modern telecommunication and storage systems. The VLSI implementation of powerful error-correcting codes and decoders with a minimum hardware resource is especially of great importance for the integration of the codes in high-speed, low consumption circuits. Such implementation requires a deep understanding of both mathematical theory of the codes and VLSI architecture design of their decoders, a dual expertise that Dr. Xinmiao Zhang was able to transcribe with high rigor and clarity in this book. From cyclic codes to the more recent binary and non-binary LDPC codes, this book equips any engineer or researcher with the necessary knowledge to implement state-of-the-art solutions."—Prof. David Declercq, Director General of Research at the ENSEA, Cergy-Pontoise, France"This book is unique in its synthesis of the advanced concepts in abstract algebra, decoding algorithms and architecture used masterfully to introduce VLSI implementations of highly sophisticated decoders of modern error correction codes."—Bane Vasic, University of Arizona

• Finite Field Arithmetic. VLSI Architecture Design Fundamentals. Root Computations for Polynomials Over Finite Fields. Reed-Solomon Encoder and Hard-Decision Decoder Architectures. Algebraic Soft-Decision Reed-Solomon Decoder Architectures. Interpolation-Based Chase and Generalized Minimum Distance Decoders. BCH Encoder and Decoder Architectures. Binary LDPC Codes and Decoder Architectures. Non-Binary LDPC Decoder Architectures.