Bokus

Andrzej J. Strojwas

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  1. VLSI Design for Manufacturing: Yield Enhancement

    VLSI Design for Manufacturing: Yield Enhancement

    1989

  2. Unified Approach for Timing Verification and Delay Fault Testing

    Unified Approach for Timing Verification and Delay Fault Testing

    1997

  3. Unified Approach for Timing Verification and Delay Fault Testing

    Unified Approach for Timing Verification and Delay Fault Testing

    2012

  4. VLSI Design for Manufacturing: Yield Enhancement

    VLSI Design for Manufacturing: Yield Enhancement

    2012