Ashish Srivastava – författare

Statistical Analysis and Optimization For VLSI: Timing and Power is a state-of-the-art book on the newly emerging field of statistical computer-aided design (CAD) tools. The very latest research in statistical timing and power analysis techniques is included, along with efforts to incorporate parametric yield as the key objective function during the design process. Included is the necessary mathematical background on techniques which find widespread use in current analysis and optimization. The emphasis is on algorithms, modeling approaches for process variability, and statistical techniques that are the cornerstone of the probabilistic CAD movement. The authors also describe recent optimization approaches to timing yield and contrast them to deterministic optimization. The work will enable new researchers in this area to come up to speed quickly, as well as provide a handy reference for those already working in CAD tool development.

Statistical Analysis and Optimization For VLSI: Timing and Power is a state-of-the-art book on the newly emerging field of statistical computer-aided design (CAD) tools. The very latest research in statistical timing and power analysis techniques is included, along with efforts to incorporate parametric yield as the key objective function during the design process. Included is the necessary mathematical background on techniques which find widespread use in current analysis and optimization. The emphasis is on algorithms, modeling approaches for process variability, and statistical techniques that are the cornerstone of the probabilistic CAD movement. The authors also describe recent optimization approaches to timing yield and contrast them to deterministic optimization. The work will enable new researchers in this area to come up to speed quickly, as well as provide a handy reference for those already working in CAD tool development.