Izzet Kale – författare

Recently, wireless LAN standards have emerged in the market. Those standards operate in various frequency ranges. To reduce component count, it is of importance to design a multi-mode frequency synthesizer that serves all wireless LAN standards including 802.11a, 802.11b and 802.11g standards. With different specifications for those standards, designing integer-based phase-locked loop frequency synthesizers can not be achieved. Fractional-N frequency synthesizers offer the solution required for a common multi-mode local oscillator. Those fractional-N synthesizers are based on delta-sigma modulators which in combination with a divider yield the fractional division required for the desired frequency of interest. In CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications, the authors outline detailed design methodology for fast frequency hopping synthesizers for RF and wireless communications applications. Great emphasis on fractional-N delta-sigma based phase locked loops from specifications, system analysis and architecture planning to circuit design and silicon implementation. The book describes an efficient design and characterization methodology that has been developed to study loop trade-offs in both open and close loop modelling techniques. This is based on a simulation platform that incorporates both behavioral models and measured/simulated sub-blocks of the chosen frequency synthesizer. The platform predicts accurately the phase noise, spurious and switching performance of the final design. Therefore excellent phase noise and spurious performance can be achieved while meeting all the specified requirements. The design methodology reduces the need for silicon re-spin enabling circuit designers to directly meet cost, performance and schedule milestones.The developed knowledge and techniques have been used in the successful design and implementation of two high speed multi-modefractional-N frequency synthesizers for the IEEE 801.11a/b/g standards. Both synthesizer designs are described in details.

The analysis of the quantization noise in delta-sigma modulators is not a trivial task. State-of-the-art analysis methods include modelling the quantization noise as a uniform distributed white noise. However, it is not uncommon to observe limit cycle oscillations and tones at the output of a delta-sigma modulator. In most of the applications, these limit cycles and tones are strictly objectionable. Such an application, for instance, is a Fractional-N PLL frequency synthesizer, where idle tones and limit cycles generated from the delta-sigma modulator directly appear in the synthesized RF waveform as spurious components. The relatively small conversion bandwidth is another important limitation of delta-sigma modulators. Due to their oversampling nature, delta-sigma modulators have been used in low frequency applications. This book presents theorems and their mathematical proofs for the exact analysis of the quantization noise in delta-sigma modulators. Extensive mathematical equations are included throughout the book to analyze both single-stage and multi-stage architectures.It has been proved that appropriately set initial conditions generate tone-free output, provided that the modulator order is at least three. These results are applied to the design of a Fractional-N PLL frequency synthesizer to produce spurious free RF waveforms. Furthermore, the book also presents time-interleaved topologies to increase the conversion bandwidth of delta-sigma modulators. The topologies have been generalized for any interleaving number and modulator order and the book contains sufficient detail to enable readers with little background in the subject to easily follow the material in it. It should be of interest to graduate students, researchers and practising circuit designers in the areas of delta-sigma based data converters and Fractional-N PLL frequency synthesizer design.

This text presents the investigation of special type of IIR polyphase filter structures combined with frequency transformation techniques used for fast, multi-rate filtering, and their application for custom fixed-point implementation. Detailed theoretical analysis of the polyphase IIR structure has been presented for two and three coefficients in the two-path arrangement. This was then generalized for arbitrary filter order and any number of paths. The use of polyphase IIR structures in decimation and interpolation is being presented and performance assessed in terms of the number of calculations required for the given filter specification and the simplicity of implementation. Specimen decimation filter designs to be used in Sigma-Delta lowpass and bandpass A/D converters are presented which prove to outperform other traditional approaches. New frequency transformation types have been suggested for both real and complex situations. A new exact multi-point frequency transformation approach for arbitrary frequency choice has been suggested and evaluated.Applying such transformations to the existing filter allows them to change their frequency response in an intuitive manner without the need of re-designing them, thus simplifying the designer's job when the specification changes during the prototyping and testing. A new "bit-flipping" algorithm has been developed to aid in filter design where the coefficient word length is constraint. Also, the standard Downhill Simplex Method (floating-point) was modified to operate with the constrained coefficient word length. Performance of both these advances is being evaluated on a number of filter cases. Novel decimation and interpolation structures have been proposed, which can be implemented very efficiently. These allow an arbitrary order IIR anti-aliasing filter to operate at the lower rate of the decimator/interpolator. Similar structures for polyphase IIR decimator/interpolator structures are being discussed too. A new approach to digital filter design and implementation has been suggested which speeds-up silicon implementation of designs developed in Matlab. The Simulink block description is converted automatically into a bit-to-bit equivalent VHDL description.This in turn can be compiled, simulated, synthesized and fabricated without the need to go through the design process twice, first algorithmic/structural design and then the implementation.

Oversampled Delta-Sigma Modulators: Analysis, Applications, and Novel Topologies presents theorems and their mathematical proofs for the exact analysis of the quantization noise in delta-sigma modulators. Extensive mathematical equations are included throughout the book to analyze both single-stage and multi-stage architectures. It has been proved that appropriately set initial conditions generate tone free output, provided that the modulator order is at least three. These results are applied to the design of a Fractional-N PLL frequency synthesizer to produce spurious free RF waveforms. Furthermore, the book also presents time-interleaved topologies to increase the conversion bandwidth of delta-sigma modulators. The topologies have been generalized for any interleaving number and modulator order. The book is full of design and analysis techniques and contains sufficient detail that enables readers with little background in the subject to easily follow the material in it.

DSP System Design presents the investigation of special type of IIR polyphase filter structures combined with frequency transformation techniques used for fast, multi-rate filtering, and their application for custom fixed-point implementation. Detailed theoretical analysis of the polyphase IIR structure has been presented for two and three coefficients in the two-path arrangement. This was then generalized for arbitrary filter order and any number of paths. The use of polyphase IIR structures in decimation and interpolation is being presented and performance assessed in terms of the number of calculations required for the given filter specification and the simplicity of implementation. Specimen decimation filter designs to be used in Sigma-Delta lowpass and bandpass A/D converters are presented which prove to outperform other traditional approaches. DSP System Design may be of interest to graduate students, researchers, and professionals circuit designers, who would require fast and low-complexity digital filters for both single and multi-rate applications, especially those with low-power specification.