Keshab K. Parhi - Böcker

Digital audio, speech recognition, cable modems, radar, high-definition television-these are but a few of the modern computer and communications applications relying on digital signal processing (DSP) and the attendant application-specific integrated circuits (ASICs). As information-age industries constantly reinvent ASIC chips for lower power consumption and higher efficiency, there is a growing need for designers who are current and fluent in VLSI design methodologies for DSP. Enter VLSI Digital Signal Processing Systems-a unique, comprehensive guide to performance optimization techniques in VLSI signal processing. Based on Keshab Parhi's highly respected and popular graduate-level courses, this volume is destined to become the standard text and reference in the field. This text integrates VLSI architecture theory and algorithms, addresses various architectures at the implementation level, and presents several approaches to analysis, estimation, and reduction of power consumption. Throughout this book, Dr. Parhi explains how to design high-speed, low-area, and low-power VLSI systems for a broad range of DSP applications. He covers pipelining extensively as well as numerous other techniques, from parallel processing to scaling and roundoff noise computation. Readers are shown how to apply all techniques to improve implementations of several DSP algorithms, using both ASICs and off-the-shelf programmable digital signal processors. The book features hundreds of graphs illustrating the various DSP algorithms, examples based on digital filters and transforms clarifying key concepts, and interesting end-of-chapter exercises that help match techniques with applications. In addition, the abundance of readily available techniques makes this an extremely useful resource for designers of DSP systems in wired, wireless, or multimedia communications. The material can be easily adopted in new courses on either VLSI digital signal processing architectures or high-performance VLSI system design. An invaluable reference and practical guide to VLSI digital signal processing. A tremendous source of optimization techniques indispensable in modern VLSI signal processing, VLSI Digital Signal Processing Systems promises to become the standard in the field. It offers a rich training ground for students of VLSI design for digital signal processing and provides immediate access to state-of-the-art, proven techniques for designers of DSP applications-in wired, wireless, or multimedia communications. Topics include:* Transformations for high speed using pipelining, retiming, and parallel processing techniques* Power reduction transformations for supply voltage reduction as well as for strength or capacitance reduction* Area reduction using folding techniques* Strategies for arithmetic implementation* Synchronous, wave, and asynchronous pipelining* Design of programmable DSPs. An Instructor's Manual presenting detailed solutions to all the problems in the book is available from the Wiley editorial department.

Adaptive filtering is commonly used in many communication applications including speech and video predictive coding, mobile radio, ISDN subscriber loops and multimedia systems. Existing adaptive filtering topologies are non-concurrent and cannot be pipelined. This text presents pipelined topologies which are useful in reducing area and power and in increasing speed. If the adaptive filter portion of a system suffers from a power-speed-area bottleneck, a solution is provided. The text is suitable reading for all users of adaptive digital filtering algorithms. Algorithm, application and integrated circuit chip designers can learn how their algorithms can be tailored and implemented with lower area and power consumption and with higher speed. The relaxed look-ahead techniques are used to design families of new topologies for many adaptive filtering applications including least mean square and lattice adaptive filters, adaptive differential pulse code modulation coders, adaptive differential vector quantizers, adaptive decision feedback equalizers and adaptive Kalman filters.Those who use adaptive filtering in communications, signal and image processing algorithms can learn the basis of relaxed look-ahead pipelining and can use their own relaxations to design pipelined topologies suitable for their applications. The book should be particularly useful to designers of communications, speech, and video applications who deal with adaptive filtering, those involved with design of modems, wireless systems, subscriber loops, beam formers, and system identification applications. It can also be used as a text for advanced courses on the topic.

The sampling rates for Digital Signal Processing (DSP) in such applications as speech, telephony, mobile radio, video, radar and sonar, ranges from 10 kHz to 100 MHz. Real-time implementation of such systems requires design of hardware that can process signal samples as these are received from the source, rather than storing them in buffers for batch-mode processing. Efficient implementation of DSP hardware demands a study of families of architectures and styles, selecting an appropriate architecture for a specific application. Digit-serial computation is proposed as an appropriate design methodology when bit-serial systems cannot meet sampling rate requirements, and where bit-parallel systems require excessive hardware. A family of implementations can be obtained by changing the digit size parameter, allowing an optimum trade-off between throughput and size. This text describes the architecture and the design and layout methods used in Parsifal - the silicon compiler developed at GEC's corporate research and development laboratory.

This text uses look-ahead transformation and constrained filter design approaches. It is shown that pipelining often reduces the roundoff noise in a digital filter. The pipelined recursive lattice and wave digital filters presented are well suited where increasing speed and reducing area or power or roundoff noise are important. Examples are wireless and cellular codec applications, where low power consumption is important, and radar and video applications, where higher speed is important. The book presents pipelining of direct-form recursive digital filters and demonstrates the usefulness of these topologies in high-speed and low-power applications. It then discusses fundamentals of scaling in the design of lattice and wave digital filters. Approaches to designing four different types of lattice digital filters are discussed, including basic, one-multiplier, normalized, and scaled normalized structures. The roundoff noise in these lattice filters is also studied.The book then presents approaches to the design of pipelined lattice digital filters for the same four types of structures, followed by pipelining of orthogonal double-rotation digital filters, which eliminate limit cycle problems. A discussion of pipelining of lattice wave digital filters follows, showing how linear phase, narrow-band, sharp-transition recursive filters can be implemented using this structure. This example is motivated by a difficult filter design problem in a wireless codec application. Finally, pipelining of ladder wave digital filters is discussed.

Addresses a wide selection of multimedia applications, programmable and custom architectures for the implementations of multimedia systems, and arithmetic architectures and design methodologies. The book covers recent applications of digital signal processing algorithms in multimedia, presents high-speed and low-priority binary and finite field arithmetic architectures, details VHDL-based implementation approaches, and more.

Pipelined Lattice and Wave Digital Recursive Filters uses look-ahead transformation and constrained filter design approaches. It is also shown that pipelining often reduces the roundoff noise in a digital filter. The pipelined recursive lattice and wave digital filters presented are well suited where increasing speed and reducing area or power or roundoff noise are important. Examples are wireless and cellular codec applications, where low power consumption is important, and radar and video applications, where higher speed is important. The book presents pipelining of direct-form recursive digital filters and demonstrates the usefulness of these topologies in high-speed and low-power applications. It then discusses fundamentals of scaling in the design of lattice and wave digital filters. Approaches to designing four different types of lattice digital filters are discussed, including basic, one-multiplier, normalized, and scaled normalized structures. The roundoff noise in these lattice filters is also studied. The book then presents approaches to the design of pipelined lattice digital filters for the same four types of structures, followed by pipelining of orthogonal double-rotation digital filters, which eliminate limit cycle problems. A discussion of pipelining of lattice wave digital filters follows, showing how linear phase, narrow-band, sharp-transition recursive filters can be implemented using this structure. This example is motivated by a difficult filter design problem in a wireless codec application. Finally, pipelining of ladder wave digital filters is discussed. Pipelined Lattice and Wave Digital Recursive Filters serves as an excellent reference and may be used as a text for advanced courses on the subject.

Digital signal processing (DSP) is used in a wide range of applications such as speech, telephone, mobile radio, video, radar and sonar. The sample rate requirements of these applications range from 10 KHz to 100 MHz. Real time implementation of these systems requires design of hardware which can process signal samples as these are received from the source, as opposed to storing them in buffers and processing them in batch mode. Efficient implementation of real­ time hardware for DSP applications requires study of families of architectures and implementation styles out of which an appropriate architecture can be selected for a specified application. To this end, the digit-serial implementation style is proposed as an appropriate design methodology for cases where bit-serial systems cannot meet the sample rate requirements, and bit-parallel systems require excessive hardware. The number of bits processed in a clock cycle is referred to as the digit-size. The hardware complexity and the achievable sample rate increase with increase in the digit-size. As special cases, a digit­ serial system is reduced to bit-serial or bit-parallel when the digit-size is selected to equal one or the word-length, respectively. A family of implementations can be obtained by changing the digit-size parameter, thus permitting an optimal trade-off between throughput and size. Because of their structured architecture, digit-serial designs lend themselves to automatic compilation from algorithmic descriptions. An implementation of this design methodology, the Parsifal silicon compiler was developed at the General Electric Corporate Research and Development laboratory.