Nikolaos Voros – författare

System Level Design of Reconfigurable Systems-on-Chip provides insight in the challenges and difficulties encountered during the design of reconfigurable Systems-on-Chip (SoCs). Reconfiguration is becoming an important part of System-on-Chip design to cope with the increasing demands for simultaneous flexibility and computational power.

The book focuses on system level design issues for reconfigurable SoCs, and provides information on reconfiguration aspects of complex SoCs and how they can be implemented in practice. It is divided in three parts. The first part provides background information and requirements on reconfigurable technologies and systems. The second one identifies existing methodological gaps, and introduces a design flow for developing reconfigurable Systems-on-Chip. The high level part of the design flow can be covered by two C++ based methodologies: one based on SystemC and one based on OCAPI-XL, both including appropriate extensions to handle reconfiguration issues. Finally, the third part of the book presents reconfigurable SoCs from the perspective of the designer, through three indicative case studies from the wireless and multimedia communication domain.

This book serves as a single-source reference to the state-of-the-art in Internet of Things (IoT) platforms, services, tools, programming languages, and applications. In particular, the authors focus on IoT-related requirements such as low-power, time-to-market, connectivity, reliability, interoperability, security, and privacy. Authors discuss the question of whether we need new IoT standardization bodies or initiatives, toward a fully connected, cyber-physical world. Coverage includes the research outcomes of several, current European projects related to IoT platforms, services, APIs, tools, and applications.

The 29 full papers and 22 short presented in this volume were carefully reviewed and selected from 78 submissions. In addition, the volume contains 9 contributions from research projects. The papers were organized in topical sections named: machine learning and neural networks; FPGA-based design and CGRA optimizations; applications and surveys; fault-tolerance, security and communication architectures; reconfigurable and adaptive architectures; design methods and fast prototyping; FPGA-based design and applications; and special session: research projects. 

Dynamic System Reconfiguration in Heterogeneous Platforms defines the MORPHEUS platform that can join the performance density advantage of reconfigurable technologies and the easy control capabilities of general purpose processors. It consists of a System-on-Chip made of a scalable system infrastructure hosting heterogeneous reconfigurable accelerators, providing dynamic reconfiguration capabilities and data-stream management capabilities.