Pavel Mach – författare

This text covers the proceedings of the NATO Advanced Research Workshop which is devoted to the technical aspects of advanced interconnections and microassembly and also includes papers on the education issues needed to prepare students for work in these areas. The future direction that such technologies may take is also dealt with. The basic issue is that the miniaturization of electronic systems continues, and performance must continue to improve. The newest packages are often based on the selection of an appropriate interconnection method. Advances in chip-scale, chip-flip, and direct chip attachments are described. Although wire bonding currently dominates the market, the consensus is that flip chip interconnection will rapidly increase its market share. Tape automated bonding is also discussed, primarily for special applications. Solder metallurgy and flip chip production technology receive attention in several papers. Solderability, reliability and fatigue of the joints are modelled, and mechanical stresses resulting from temperature cycling are reported. Multichip module and thick-film hybrid substrate interconnections are reported in several papers.These include thick and thin film metals, as well as low temperature polymer inks. Several papers describe diffusion and other metallurgical interactions in thick film surfaces.

MICROELECTRONIC INTERCONNECTIONS AND MICROASSEMBL Y WORKSHOP 18-21 May 1996, Prague, Czech Republic Conference Organizers: George Harman, NIST (USA) and Pavel Mach (Czech Republic) Summary of the Technical Program Thirty two presentations were given in eight technical sessions at the Workshop. A list of these sessions and their chairpersons is attached below. The Workshop was devoted to the technical aspects of advanced interconnections and microassembly, but also included papers on the education issues required to prepare students to work in these areas. In addition to new technical developments, several papers presented overviews predicting the future directions of these technologies. The basic issue is that electronic systems will continue to be miniaturized and at the same time performance must continue to improve. Various industry roadmaps were discussed as well as new smaller packaging and interconnection concepts. The newest chip packages are often based on the selection of an appropriate interconnection method. An example is the chip-scale package, which has horizontal (x-y) dimensions,;; 20% larger than the actual silicon chip itself. The chip is often flip-chip connected to a micro ball-grid-array, but direct chip attach was described also. Several papers described advances in the manufacture of such packages.