Per Stenström – författare

This book constitutes the proceedings of the 13th International Symposium on Advanced Parallel Processing Technologies, APPT 2019, held in Tianjin, China, in August 2019.The 11 full papers presented in this volume were carefully reviewed and selected from 35 submissions. The papers are organized in topical sections named: System Support for Neural Networks; Scheduling and File Systems; Optimization and Parallelization; Security and Algorithms.

This synthesis lecture presents the current state-of-the-art in applying low-latency, lossless hardware compression algorithms to cache, memory, and the memory/cache link. There are many non-trivial challenges that must be addressed to make data compression work well in this context. First, since compressed data must be decompressed before it can be accessed, decompression latency ends up on the critical memory access path. This imposes a significant constraint on the choice of compression algorithms. Second, while conventional memory systems store fixed-size entities like data types, cache blocks, and memory pages, these entities will suddenly vary in size in a memory system that employs compression. Dealing with variable size entities in a memory system using compression has a significant impact on the way caches are organized and how to manage the resources in main memory. We systematically discuss solutions in the open literature to these problems. Chapter 2 provides the foundations of data compression by first introducing the fundamental concept of value locality. We then introduce a taxonomy of compression algorithms and show how previously proposed algorithms fit within that logical framework. Chapter 3 discusses the different ways that cache memory systems can employ compression, focusing on the trade-offs between latency, capacity, and complexity of alternative ways to compact compressed cache blocks. Chapter 4 discusses issues in applying data compression to main memory and Chapter 5 covers techniques for compressing data on the cache-to-memory links. This book should help a skilled memory system designer understand the fundamental challenges in applying compression to the memory hierarchy and introduce him/her to the state-of-the-art techniques in addressing them.

This book constitutes the refereed proceedings of the Second International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2007, held in Ghent, Belgium, in January 2007. The 19 revised full papers presented together with one invited keynote paper were carefully reviewed and selected from 65 submissions. The papers are organized in topical sections.

This highly relevant and up-to-the-minute book constitutes the refereed proceedings of the Third International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Goteborg, Sweden, January 27-29, 2008. The 25 revised full papers presented together with 1 invited keynote paper were carefully reviewed and selected from 77 submissions. The papers are organized into topical sections on a number of key subjects in the field.

1 2 Per Stenstro ..m and David Whalley 1 Chalmers University of Technology, Sweden 2 Florida State University, U.S.A. In January2007,the secondedition in the series of International Conferenceson High-Performance Embedded Architectures andCompilers (HiPEAC'2007)was held in Ghent,Belgium.We were fortunate to attract around70 submissions of whichonly19wereselected forpresentation.Amongthese,weaskedtheauthors ofthe?vemost highly rated contributionsto make extended versions ofthem. They all accepted to do that andtheirarticles appear in this section ofthe second volume. The?rstarticlebyKeramidas,Xekalakis,andKaxirasfocusesontheincreased power consumption in set-associativecaches.They presenta novel approach to reduce dynamicpower that leverages on the previously proposed cache decay approach that has been shown to reduce static (or leakage) power. In the secondarticlebyMagarajan,Gupta,andKrishnaswamythe focus ison techniques to encrypt data in memory to preservedata integrity. The problem with previous techniques is that the decryption latency ends up on the critical memory access path. Especially in embedded processors,caches are small and it isdi?cultto hide the decryption latency.The authors propose a compiler-based strategy that manages to reduce the impact of the decryption time signi?cantly. The thirdarticlebyKluyskensandEeckhoutfocusesondetailedarchitectural simulation techniques.It is well-known that they are ine?cientandaremedy to the problem isto use sampling.When usingsampling,onehastowarm up memory structures such as caches andbranch predictors.Thispaper introduces a noveltechnique calledBranchHistoryMatchingfore?cient warmupofbranch predictors. The fourth articlebyBhadauria,McKee,Singh, and Tyson focuses on static power consumptioninlarge caches.Theyintroduce a reuse-distance drowsy cache mechanism that issimpleas well as e?ective in reducingthestaticpower in caches.

Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This third issue contains 14 papers carefully reviewed and selected out of numerous submissions and is divided into four sections. The first section contains the top four papers from the Third International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Göteborg, Sweden, in January 2008. The second section consists of four papers from the 8th MEDEA Workshop held in conjunction with PACT 2007 in Brasov, Romania, in September 2007. The third section contains two regular papers and the fourth section provides a snapshot from the First Workshop on Programmability Issues for Multicore Computers, MULTIPROG, held in conjunction with HiPEAC 2008.