Philip R. Moorby – författare

XV Acknowledgments xvii Chapter 1 Verilog - A Tutorial Introduction Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 Behavioral Modeling of Combinational Circuits II Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 Behavioral Modeling of Clocked Sequential Circuits 14 Modeling Finite State Machines IS Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment("

xv From the Old to the New xvii Acknowledgments xxi 1 Verilog – A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("

xv From the Old to the New xvii Acknowledgments xxi 1 Verilog – A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("

The Verilog language is a hardware description language which provides a means of specifying a digital system at a wide range of levels of abstraction. The language supports the early conceptual stages of design with its behavioral level of abstraction, and the later implementation stages with its structural level of abstraction. The language provides hierarchical constructs, allowing the designer to control the complexity of a description. Verilog was originally designed in the winter of 1983/84 as a proprietary verification/simulation product. Since then, several other proprietary analysis tools have been developed around the language, including a fault simulator and a timing analyzer; the language being instrumental in providing consistency across these tools. Now, the language is openly available for any tool to read and write. This book introduces the language. It is sometimes difficult to separate the language from the simulator tool because the dynamic aspects of the language are defined by the way the simulator works. Where possible, we have stayed away from simulator-specific details and concentrated on design specification, but have included enough information to be able to have working executable models. The book takes a tutorial approach to presenting the language.

The Verilog language is a hardware description language which provides a means of specifying a digital system at a wide range of levels of abstraction. The language supports the early conceptual stages of design with its behavioral level of abstraction, and the later implementation stages with its structural level of abstraction. The language provides hierarchical constructs, allowing the designer to control the complexity of a description. Verilog was originally designed in the winter of 1983/84 as a proprietary verification/simulation product. Since then, several other proprietary analysis tools have been developed around the language, including a fault simulator and a timing analyzer; the language being instrumental in providing consistency across these tools. Now, the language is openly available for any tool to read and write. This book introduces the language. It is sometimes difficult to separate the language from the simulator tool because the dynamic aspects of the language are defined by the way the simulator works. Where possible, we have stayed away from simulator-specific details and concentrated on design specification, but have included enough information to be able to have working executable models. The book takes a tutorial approach to presenting the language.

Why learn and use Verilog if you''re a student, beginning designer, or leading edge systems designer? The naive would ignore Verilog and "standardize" by using VHDL, the result of a decade-long committee design process. A single language for the whole world would appear to: ease the training of designers and others who use descriptions, increase tool competition to lower costs, and increase design sharing and library usage. Further, the U. S. Department of Defense (DOD) mandated its use for design description Mandated standards rarely are best, and often not very good. Competition is good because it encourages rapid evolution. Also, we know that evolved, de facto standards embodied in a time-tested product based on initial conceptual clarity from one person or organization versus de jure standards coming from large committees or government mandates are often preferred. A standard must be "open" so that many others can use it, build on it, and compete to make it better. One only has to compare: C, C++, and FORTRAN versus ADA (DOD''s mandated language), PLl; TCP/IP versus OSI; the Intel X86 or PowerPC microprocessors versus DOD''s many architectures; Windows versus the many UNIX dialects; and various industry buses versus DOD''s Futurebus. Verilog, introduced in 1985, was developed by one person, Phil Moorby at Gate­ way Design Automation. It was Phil''s third commercial logic simulator.

•• XVII Acknowledgments CHAPTER 1 Verilog - A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the NAND Latch 4 Module Hleral''Chy 6 The Counter 7 Components of the Counter 9 A Clock for the System 10 Tying the Whole Circuit Together 11 Using An Alternate Description of the Flip Flop 13 Behavioral Modeling 1 S A Behavioral Model of the m16 Counter 16 Mixing Structure and Behavior 18 Assignment Statements 22 Summary on Mixing Behavioral and Structural Descriptions 23 Creating a Testbench For a Module 24 Summary 2S Tutorial Guide to Formal Syntax Specification 26 Exercises 30 CHAPTER 2 Behavioral Modeling 33 Process Model 33 If-Then-Else 3S Where Does The ELSE Belong? 39 The Conditional Operator 41 Loops 41 Four Basic Loop Statements 42 Exiting Loops on Exceptional Conditions 45 Multi-way branching 46 If-Else-If 46 Case 46 Comparison of Case and If-Else-If 48 viii The Verilog Hardware Description Language Casez and Casex 49 Functions and Tasks SO Tasks 52 Functions 55 A Structural View 57 Rules of Scope and Hierarchical Names S9 Rules of Scope 60 Hierarchical Names 62 Summary 63 Exerdses 63 CHAPTER 3 Concurrent Processes 6S Concu"ent Processes 6S Events 67 Event Control Statement 67 Named Events 69 The Walt Statement 72 A Complete Producer-Consumer Handshake 74 Comparison of the Wait and While Statements 77 Comparison of Wait and Event Control Statements 78 A Concu"ent Process Example 78 Disabling Named Blocks 84 Intra-Assignment Control and Timing Events 87 Procedural Continuous Assignment 90