Rohit Dhiman – författare

The incessant scaling of complementary metal-oxide semiconductor (CMOS) technology has resulted in significant performance improvements in very-large-scale integration (VLSI) design techniques and system architectures. This trend is expected to continue in the future, but this requires breakthroughs in the design of nano-CMOS and post-CMOS technologies. Nanoelectronics refers to the possible future technologies beyond conventional CMOS scaling limits. This volume addresses the current state-of-the-art nanoelectronic technologies and presents potential options for next-generation integrated circuits.

Nanoelectronics for Next-generation Integrated Circuits is a useful reference guide for researchers, engineers, and advanced students working on the frontier of the design and modeling of nanoelectronic devices and their integration aspects with future CMOS circuits. This comprehensive volume eloquently presents the design methodologies for spintronics memories, quantum-dot cellular automata, and post-CMOS FETs, including applications in emerging integrated circuit technologies.

The incessant scaling of complementary metal-oxide semiconductor (CMOS) technology has resulted in significant performance improvements in very-large-scale integration (VLSI) design techniques and system architectures. This trend is expected to continue in the future, but this requires breakthroughs in the design of nano-CMOS and post-CMOS technologies. Nanoelectronics refers to the possible future technologies beyond conventional CMOS scaling limits. This volume addresses the current state-of-the-art nanoelectronic technologies and presents potential options for next-generation integrated circuits.

Nanoelectronics for Next-generation Integrated Circuits is a useful reference guide for researchers, engineers, and advanced students working on the frontier of the design and modeling of nanoelectronic devices and their integration aspects with future CMOS circuits. This comprehensive volume eloquently presents the design methodologies for spintronics memories, quantum-dot cellular automata, and post-CMOS FETs, including applications in emerging integrated circuit technologies.

The book provides a detailed analysis of issues related to sub-threshold interconnect performance from the perspective of analytical approach and design techniques. Particular emphasis is laid on the performance analysis of coupling noise and variability issues in sub-threshold domain to develop efficient compact models. The proposed analytical approach gives physical insight of the parameters affecting the transient behavior of coupled interconnects. Remedial design techniques are also suggested to mitigate the effect of coupling noise. The effects of wire width, spacing between the wires, wire length are thoroughly investigated. In addition, the effect of parameters like driver strength on peak coupling noise has also been analyzed. Process, voltage and temperature variations are prominent factors affecting sub-threshold design and have also been investigated. The process variability analysis has been carried out using parametric analysis, process corner analysis and Monte Carlo technique. The book also provides a qualitative summary of the work reported in the literature by various researchers in the design of digital sub-threshold circuits. This book should be of interest for researchers and graduate students with deeper insights into sub-threshold interconnect models in particular. In this sense, this book will best fit as a text book and/or a reference book for students who are initiated in the area of research and advanced courses in nanotechnology, interconnect design and modeling.