Sao-Jie Chen – författare

In the market of wireless communication, high data-rate transmission and high spectral efficiency have been the trend. The IEEE 802.11 a/g standards working at 5GHz/2.4GHz ISM bands can support data rate up to 54Mbits/s using OFDM modulation. The newly proposed 802.11n technology now uses 64-QAM to achieve higher spectral efficiency. The DVB and many other systems will also use QAM for its data transmission.The cost of achieving this higher spectral efficiency using higher order QAM is that the transmitter and receiver requires a higher signal to noise ratio (SNR) with the same level of error rate performance (relative to a baseline BPSK, QPSK and other systems). One of the dominant vectors on SNR degradation is I/Q image rejection (I/Q gains and phases imbalance).There are a lot of factors that degrade the matching of gains and phases between I/Q signals: the instinct layout mismatch, the random mismatch of the devices, the different temperatures over the I/Q signal paths. IQ Calibration Techniques For CMOS Radio Transceivers describes a fully-analog compensation technique without baseband circuitry to control the calibration process. This book will use an 802.11g transceiver design as an example to give a detailed description on the I/Q gains and phases imbalance auto-calibration mechanism.

At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture.In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability.

Hardware Software Co-Design of a Multimedia SOC Platform is one of the first of its kinds to provide a comprehensive overview of the design and implementation of the hardware and software of an SoC platform for multimedia applications. Topics covered in this book range from system level design methodology, multimedia algorithm implementation, a sub-word parallel, single-instruction-multiple data (SIMD) processor design, and its virtual platform implementation, to the development of an SIMD parallel compiler as well as a real-time operating system (RTOS). Hardware Software Co-Design of a Multimedia SOC Platform is written for practitioner engineers and technical managers who want to gain first hand knowledge about the hardware-software design process of an SoC platform. It offers both tutorial-like details to help readers become familiar with a diverse range of subjects, and in-depth analysis for advanced readers to pursue further.

This book provides a comprehensive survey of recent progress in the design and implementation of Networks-on-Chip. It addresses a wide spectrum of on-chip communication problems, ranging from physical, network, to application layers. Specific topics that are explored in detail include packet routing, resource arbitration, error control/correction, application mapping, and communication scheduling. Additionally, a novel bi-directional communication channel NoC (BiNoC) architecture is described, with detailed explanation. Written for practicing engineers in need of practical knowledge about the design and implementation of networks-on-chip; Includes tutorial-like details to introduce readers to a diverse range of NoC designs, as well as in-depth analysis for designers with NoC experience to explore advanced issues; Describes a variety of on-chip communication architectures, including a novel bi-directional communication channel NoC. From the Foreword:Overall this book shows important advances over the state of the art that will affect future system design as well as R&D in tools and methods for NoC design. It represents an important reference point for both designers and electronic design automation researchers and developers.--Giovanni De Micheli

This book provides a comprehensive survey of recent progress in the design and implementation of Networks-on-Chip. It addresses a wide spectrum of on-chip communication problems, ranging from physical, network, to application layers. Specific topics that are explored in detail include packet routing, resource arbitration, error control/correction, application mapping, and communication scheduling. Additionally, a novel bi-directional communication channel NoC (BiNoC) architecture is described, with detailed explanation. Written for practicing engineers in need of practical knowledge about the design and implementation of networks-on-chip; Includes tutorial-like details to introduce readers to a diverse range of NoC designs, as well as in-depth analysis for designers with NoC experience to explore advanced issues; Describes a variety of on-chip communication architectures, including a novel bi-directional communication channel NoC. From the Foreword:Overall this book shows important advances over the state of the art that will affect future system design as well as R&D in tools and methods for NoC design. It represents an important reference point for both designers and electronic design automation researchers and developers.--Giovanni De Micheli

In the market of wireless communication, high data-rate transmission and high spectral efficiency have been the trend. The IEEE 802.11 a/g standards working at 5GHz/2.4GHz ISM bands can support data rate up to 54Mbits/s using OFDM modulation. The newly proposed 802.11n technology now uses 64-QAM to achieve higher spectral efficiency. The DVB and many other systems will also use QAM for its data transmission.The cost of achieving this higher spectral efficiency using higher order QAM is that the transmitter and receiver requires a higher signal to noise ratio (SNR) with the same level of error rate performance (relative to a baseline BPSK, QPSK and other systems). One of the dominant vectors on SNR degradation is I/Q image rejection (I/Q gains and phases imbalance).There are a lot of factors that degrade the matching of gains and phases between I/Q signals: the instinct layout mismatch, the random mismatch of the devices, the different temperatures over the I/Q signal paths. IQ Calibration Techniques For CMOS Radio Transceivers describes a fully-analog compensation technique without baseband circuitry to control the calibration process. This book will use an 802.11g transceiver design as an example to give a detailed description on the I/Q gains and phases imbalance auto-calibration mechanism.

At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture.In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability.