Wen-mei W. Hwu – författare
521 kr
Skickas inom 10-15 vardagar
Heterogeneous Systems Architecture - a new compute platform infrastructure presents a next-generation hardware platform, and associated software, that allows processors of different types to work efficiently and cooperatively in shared memory from a single source program. HSA also defines a virtual ISA for parallel routines or kernels, which is vendor and ISA independent thus enabling single source programs to execute across any HSA compliant heterogeneous processer from those used in smartphones to supercomputers.
The book begins with an overview of the evolution of heterogeneous parallel processing, associated problems, and how they are overcome with HSA. Later chapters provide a deeper perspective on topics such as the runtime, memory model, queuing, context switching, the architected queuing language, simulators, and tool chains. Finally, three real world examples are presented, which provide an early demonstration of how HSA can deliver significantly higher performance thru C++ based applications. Contributing authors are HSA Foundation members who are experts from both academia and industry. Some of these distinguished authors are listed here in alphabetical order: Yeh-Ching Chung, Benedict R. Gaster, Juan G�mez-Luna, Derek Hower, Lee Howes, Shih-Hao HungThomas B. Jablin, David Kaeli,Phil Rogers, Ben Sander, I-Jui (Ray) Sung.
Provides clear and concise explanations of key HSA concepts and fundamentals by expert HSA Specification contributors Explains how performance-bound programming algorithms and application types can be significantly optimized by utilizing HSA hardware and software features Presents HSA simply, clearly, and concisely without reading the detailed HSA Specification documents Demonstrates ideal mapping of processing resources from CPUs to many other heterogeneous processors that comply with HSA Specifications
811 kr
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Programming Massively Parallel Processors: A Hands-on Approach shows both students and professionals alike the basic concepts of parallel programming and GPU architecture. Concise, intuitive, and practical, it is based on years of road-testing in the authors' own parallel computing courses. Various techniques for constructing and optimizing parallel programs are explored in detail, while case studies demonstrate the development process, which begins with computational thinking and ends with effective and efficient parallel programs. The new edition includes updated coverage of CUDA, including the newer libraries such as CuDNN. New chapters on frequently used parallel patterns have been added, and case studies have been updated to reflect current industry practices.
Parallel Patterns Introduces new chapters on frequently used parallel patterns (stencil, reduction, sorting) and major improvements to previous chapters (convolution, histogram, sparse matrices, graph traversal, deep learning) Ampere Includes a new chapter focused on GPU architecture and draws examples from recent architecture generations, including Ampere Systematic Approach Incorporates major improvements to abstract discussions of problem decomposition strategies and performance considerations, with a new optimization checklist
914 kr
Kommande
Performance Analysis and Tuning for General Purpose Graphics Processing Units (GPGPU)
326 kr
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High Performance Embedded Architectures and Compilers
First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings
556 kr
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