Writing Testbenches: Functional Verification of HDL Models

AvJanick Bergeron

Inbunden, Engelska, 2003

2 416 kr

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2 346 kr

Beskrivning

This second edition presents the most up-to-date verification techniques to produce fully functional first silicon ASICs, systems-on-a-chip (SoC), boards and entire systems. Topics included are: discussions on openvera and e; approaches for writing constrainable random stimulus generators; strategies for making testbenches self-checking; a clear blueprint of a verification process that aims for first time success; recent advances in functional verification such as coverage-driven verification process; VHDL and Verilog language semantics; the semantics are presented in new verification-oriented languages; techniques for applying stimulus and monitoring the response of a design; behavioural modelling using non-synthesizeable constructs and coding style; and updated for Verilog 2001.

Produktinformation

Utgivningsdatum:2003-02-28
Mått:162 x 241 x 29 mm
Vikt:800 g
Format:Inbunden
Språk:Engelska
Antal sidor:478
Upplaga:2
Förlag:Kluwer Academic Publishers
ISBN:9781402074011

Utforska kategorier

Systemvetenskap och AI inom Data och IT
Programspråk inom Data och IT

Recensioner i media

"Brilliant. Janick Bergeron has built on his ground-breaking first version of Writing Testbenches in this second edition..." (Grant Martin, Fellow, Cadence Berkeley Labs) "In the latest edition, Mr. Bergeron continues to keep pace with the industry while providing world-class solutions to the verification problem..." (Chris Macinonski, Senior Engineer, Qualis Design Corp.) "Many companies out there now owe their current verification methodologies to this book. From it they have learned the secrets of efficiency, effectiveness and re-use as they apply to verification..." (Brian Bailey, Chief Technologist, Mentor Graphics Corp.) "A must have bible for understanding verification issues and techniques with HDLs and HVLs, and for writing effective, readable and reusable testbenches within a best-in-class verification process." (Ben Cohen, VhdlCohen Training)

Innehållsförteckning

1 What is Verification?.- What is a Testbench?.- The Importance of Verification.- Reconvergence Model.- The Human Factor.- What Is Being Verified?.- Functional Verification Approaches.- Testing Versus Verification.- Design and Verification Reuse.- The Cost of Verification.- Summary.- 2 Verification Tools.- Linting Tools.- Simulators.- Verification Intellectual Property.- Waveform Viewers.- Functional Coverage.- Verification Languages.- Assertions.- Revision Control.- Issue Tracking.- Metrics.- Summary.- 3 The Verification Plan.- The Role of the Verification Plan.- Levels of Verification.- Verification Strategies.- From Specification to Features.- Directed Testbenches Approach.- Coverage-Driven Random-Based Approach.- Summary.- 4 High-Level Modeling.- Behavioral versus RTL Thinking.- You Gotta Have Style!.- Structure of Behavioral Code.- Data Abstraction.- Object-Oriented Programming.- Aspect-Oriented Programming.- The Parallel Simulation Engine.- Race Conditions.- Verilog Portability Issues.- Summary.- 5 Stimulus and Response.- Reference Signals.- Simple Stimulus.- Simple Output.- Complex Stimulus.- Bus-Functional Models.- Response Monitors.- Transaction-Level Interface.- Summary.- 6 Architecting Testbenches.- Test Harness.- VHDL Test Harness.- Design Configuration.- Self-Checking Testbenches.- Directed Stimulus.- Random Stimulus.- Summary.- 7 Simulation Management.- Behavioral Models.- Pass or Fail?.- Managing Simulations.- Regression.- Summary.- Appendix A Coding Guidelines.- Directory Structure.- VHDL Specific.- Verilog Specific.- General Coding Guidelines.- Comments.- Layout.- Syntax.- Debugging.- Naming Guidelines.- Capitalization.- Identifiers.- Constants.- HDL & HVL Specific.- Filenames.- HDL Coding Guidelines.- Structure.- Layout.- VHDL Specific.- Verilog Specific.- Appendix B Glossary.- Afterwords.