Brajesh Kumar Kaushik received his Doctorate of Philosophy (PhD) in 2007 from Indian Institute of Technology Roorkee, India. He served Vinytics Peripherals Pvt. Ltd., Delhi, as a Research and Development engineer in microprocessor, microcontroller, and DSP processor-based system design. He joined Department of Electronics and Communication Engineering, Indian Institute of Technology, Roorkee, as Assistant Professor in December 2009; and since April 2014 he has been an Associate Professor. He has extensively published in several national and international journals and conferences. He is a reviewer of many international journals belonging to various organizations and publishers including IEEE, IET, Elsevier, Springer, Taylor & Francis, Emerald, ETRI, and PIER. He has served as General Chair, Technical Chair, and Keynote Speaker of many reputed international and national conferences. Dr. Kaushik is Senior Member of IEEE and member of many expert committees constituted by government and nongovernment organizations. He holds the position of Editor and Editor-in-Chief of various journals in the field of VLSI and microelectronics. He is Editor-in-Chief of International Journal of VLSI Design & Communication Systems (VLSICS), AIRCC Publishing Corporation. He also holds the position of Editor of Microelectronics Journal (MEJ), Elsevier Inc.; Journal of Engineering, Design and Technology (JEDT), Emerald Group Publishing Limited; and Journal of Electrical and Electronics Engineering Research (JEEER), Academic Journals. He has received many awards and recognitions from the International Biographical Center (IBC), Cambridge. His name has been listed in Marquis Who’s Who in Science and Engineering® and Marquis Who’s Who in the World®. His research interests are in the areas of high-speed interconnects, low-power VLSI design, carbon nanotube-based designs, organic electronics. FinFET device circuit co-design, electronic design automation (EDA), and spintronics-based devices and circuits.

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• Introduction. Packaging techniques of future ICs. Integrated architectures. Summary. Through Silicon Vias: Materials, Properties and Fabrication. Introduction. History of graphene material. Carbon nanotube. Graphene nanoribbon. Properties of TSV. Fabrication of TSVs. Challenges for the TSV implementations. Summary. Copper Based TSVs. Introduction. Physical configuration. Modelling of Cu based TSVs. Performance analysis of Cu based TSVs. Summary. Carbon Nanotube Based TSVs. Introduction. Physical configuration. Modelling. Performance analysis of CNT based TSVs. Summary. Mixed CNT Bundled Based TSVs. Introduction. Configurations of mixed CNT bundled TSVs. Modelling of MCB based TSVs. Signal integrity analysis of MCB based TSVs. Summary. Graphene Nanoribbon Based TSVs. Introduction. Configurations of GNR based TSVs. Fabrication challenges and limitations. Modelling of GNR based TSVs with smooth edges. Modelling of GNR based TSVs with rough edges. Signal integrity analysis of GNR based TSVs. Summary. Liners in TSVs. Introduction. Types of liners and their impact on performance. Fabrication challenges. Modelling of CNT bundled TSV with SiO2 and polymer liners. Impact of polymer liners on delay. Summary.