Handbook of 3D Integration, Volume 3

Philip Garrou is a consultant and expert witness in the field of IC packaging materials and applications, prior to which he was Dir. of Technology and Business Dev. for Dow Chemicals' Electronic Materials business. Dr. Garrou is a Fellow of IEEE and IMAPS and served as President of the IEEE CPMT Society and IMAPS. He has co-authored 3 microelectronics texts and 100+ publications. He is Assoc. Ed. and author of the weekly blog "Insights from the Leading Edge" for Solid State Technology and has co-authored 3DIC reports for both TechSearch and Yole.Mitsumasa Koyanagi is Professor in the Graduate School of Engineering at Tohoku University, Japan. After his PhD in electrical engineering he joined the Central Research Laboratory of Hitachi where he was engaged in the research on semiconductor memories. After a three-year stay at the Xerox Palo Alto Research Center in California, USA, he became Professor in the Research Center for Integrated Systems at Hiroshima University, Japan. Mitsumasa Koyanagi received numerous awards, including the Solid-State Devices and Materials Award.Peter Ramm is head of the department Heterogeneous System Integration of Fraunhofer EMFT in Munich, Germany, where he is responsible for the key competence "Si Processes, Device and 3D Integration". He received the physics and Dr. rer. nat. degrees from the University of Regensburg and subsequently worked for Siemens in the DRAM facility where he was responsible for the process integration. In 1988 he joined Fraunhofer IFT in Munich, focusing for more than 25 years on 3D integration technologies. Peter Ramm is co-author of over 100 publications and 24 patents and editor of Wiley's "Handbook of Wafer Bonding". He received the "Ashman Award 2009" from IMAPS "For Pioneering Work on 3D IC Stacking and Integration".

• List of Contributors xvii1 3D IC Integration Since 2008 1Philip Garrou, Peter Ramm, and Mitsumasa Koyanagi1.1 3D IC Nomenclature 11.2 Process Standardization 21.3 The Introduction of Interposers (2.5D) 41.4 The Foundries 61.4.1 TSMC 61.4.2 UMC 71.4.3 GlobalFoundries 71.5 Memory 71.5.1 Samsung 71.5.2 Micron 81.5.3 Hynix 91.6 The Assembly and Test Houses 91.7 3D IC Application Roadmaps 10References 112 Key Applications and Market Trends for 3D Integration and Interposer Technologies 13Rozalia Beica, Jean-Christophe Eloy, and Peter Ramm2.1 Introduction 132.2 Advanced Packaging Importance in the Semiconductor Industry is Growing 162.3 3D Integration-Focused Activities – The Global IP Landscape 182.4 Applications, Technology, and Market Trends 22References 323 Economic Drivers and Impediments for 2.5D/3D Integration 33Philip Garrou3.1 3D Performance Advantages 333.2 The Economics of Scaling 333.3 The Cost of Future Scaling 343.4 Cost Remains the Impediment to 2.5D and 3D Product Introduction 373.4.1 Required Economics for Interposer Use in Mobile Products 383.4.2 Silicon Interposer Pricing 38References 404 Interposer Technology 41Venky Sundaram and Rao R. Tummala4.1 Definition of 2.5D Interposers 414.2 Interposer Drivers and Need 424.3 Comparison of Interposer Materials 444.4 Silicon Interposers with TSV 454.5 Lower Cost Interposers 484.5.1 Glass Interposers 484.5.1.1 Challenges in Glass Interposers 494.5.1.2 Small-Pitch Through-Package Via Hole Formation and Ultrathin Glass Handling 494.5.1.3 Metallization of Glass TPV 514.5.1.4 Reliability of Copper TPVs in Glass Interposers 524.5.1.5 Thermal Dissipation of Glass 534.5.1.6 Glass Interposer Fabrication with TPV and RDL 534.5.2 Low-CTE Organic Interposers 534.5.3 Polycrystalline Silicon Interposer 554.5.3.1 Polycrystalline Silicon Interposer Fabrication Process 564.6 Interposer Technical and Manufacturing Challenges 574.7 Interposer Application Examples 584.8 Conclusions 60References 615 TSV Formation Overview 65Dean Malta5.1 Introduction 655.2 TSV Process Approaches 675.2.1 TSV-Middle Approach 685.2.2 Backside TSV-Last Approach 685.2.3 Front-Side TSV-Last Approach 695.3 TSV Fabrication Steps 705.3.1 TSV Etching 705.3.2 TSV Insulation 715.3.3 TSV Metallization 715.3.4 Overburden Removal by CMP 725.3.5 TSV Anneal 735.3.6 Temporary Carrier Wafer Bonding and Debonding 745.3.7 Wafer Thinning and TSV Reveal 745.4 Yield and Reliability 75References 766 TSV Unit Processes and Integration 79Sesh Ramaswami6.1 Introduction 796.2 TSV Process Overview 806.3 TSV Unit Processes 826.3.1 Etching 826.3.2 Insulator Deposition with CVD 836.3.3 Metal Liner/Barrier Deposition with PVD 846.3.4 Via Filling by ECD of Copper 846.3.5 CMP of Copper 856.3.6 Temporary Bonding between Carrier and Device Wafer 866.3.7 Wafer Backside Thinning 866.3.8 Backside RDL 876.3.9 Metrology, Inspection, and Defect Review 876.4 Integration and Co-optimization of Unit Processes in Via Formation Sequence 886.5 Co-optimization of Unit Processes in Backside Processing and Via-Reveal Flow 896.6 Integration and Co-optimization of Unit Processes in Via-Last Flow 916.7 Integration with Packaging 926.8 Electrical Characterization of TSVs 926.9 Conclusions 96References 977 TSV Formation at ASET 99Hiroaki Ikeda7.1 Introduction 997.2 Via-Last TSV for Both D2D and W2W Processes in ASET 1037.3 TSV Process for D2D 1057.3.1 Front-Side Bump Forming 1067.3.2 Attach WSS and Thinning 1067.3.3 Deep Si Etching from the Backside 1077.3.4 Liner Deposition 1077.3.5 Removal of SiO 2 at the Bottom of Via 1077.3.6 Barrier Metal and Seed Layer Deposition by PVD 1107.3.7 Cu Electroplating 1107.3.8 Cmp 1107.3.9 Backside Bump 1117.3.10 Detach WSS 1117.3.11 Dicing 1127.4 TSV Process for W2W 1137.4.1 Polymer Layer Coat and Development 1147.4.2 Barrier Metal and Seed Layer Deposition 1147.4.3 Cu Plating 1147.4.4 CMP 1157.4.5 First W2W Stacking (Face to Face) 1167.4.6 Wafer Thinning and Deep Si Etching 1167.4.7 TSV Liner Deposition and SiO2 Etching of Via Bottom 1177.4.8 Barrier Metal and Seed Layer Deposition and Cu Plating 1177.4.9 CMP 1177.4.10 Next W2W Stacking 1187.5 Conclusions 119References 1198 Laser-Assisted Wafer Processing: New Perspectives in Through-Substrate Via Drilling and Redistribution Layer Deposition 121Marc B. Hoppenbrouwers, Gerrit Oosterhuis, Guido Knippels, and Fred Roozeboom8.1 Introduction 1218.2 Laser Drilling of TSVs 1218.2.1 Cost of Ownership Comparison 1218.2.2 Requirements for an Industrial TSV Laser Driller 1238.2.3 Drilling Strategy 1248.2.3.1 Mechanical 1248.2.3.2 Optical 1258.2.4 Experimental Drilling Results 1268.3 Direct-Write Deposition of Redistribution Layers 1268.3.1 Introduction on Redistribution Layers 1268.3.2 Direct-Write Characteristics 1278.3.3 Direct-Write Laser-Induced Forward Transfer 1288.3.4 LIFT Results 1308.4 Conclusions and Outlook 131References 1329 Temporary Bonding Material Requirements 135Rama Puligadda9.1 Introduction 1359.2 Technology Options 1369.2.1 Tapes and Waxes 1369.2.2 Chemical Debonding 1369.2.3 Thermoplastic Bonding Material and Slide Debonding 1369.2.4 Debonding Using Release Layers 1379.3 Requirements of a Temporary Bonding Material 1389.4 Considerations for Successful Processing 1399.4.1 Application of the Temporary Bonding Adhesive to the Device Wafer and Bonding to Carrier 1399.4.2 Moisture and Contaminants on Surface 1399.4.3 Total Thickness Variation 1409.4.4 Squeeze Out 1409.5 Surviving the Backside Process 1419.5.1 Edge Trimming 1429.5.2 Edge Cleaning 1429.5.3 Temperature Excursions in Plasma Processes 1439.5.4 Wafer Warpage due to CTE Mismatch 1439.6 Debonding 1449.6.1 Debonding Parameters in Slide-Off Debonding 1449.6.2 Mechanical Damage to Interconnects 144References 14510 Temporary Bonding and Debonding – An Update on Materials and Methods 147Wilfried Bair10.1 Introduction 14710.2 Carrier Selection for Temporary Bonding 14810.3 Selection of Temporary Bonding Adhesives 15110.4 Bonding and Debonding Processes 15210.5 Equipment and Process Integration 155References 15611 ZoneBOND 1 : Recent Developments in Temporary Bonding and Room-Temperature Debonding 159Thorsten Matthias, J€urgen Burggraf, Daniel Burgstaller, Markus Wimplinger, and Paul Lindner11.1 Introduction 15911.2 Thin Wafer Processing 15911.2.1 Thin Wafer Total Thickness Variation 16111.2.2 Wafer Alignment 16311.3 ZoneBOND Room-Temperature Debonding 16311.4 Conclusions 165References 16612 Temporary Bonding and Debonding at TOK 167Shoji Otaka12.1 Introduction 16712.2 Zero Newton Technology 16812.2.1 The Wafer Bonder 16812.2.2 The Wafer Debonder 17012.2.3 The Wafer Bonder and Debonder Equipment Lineups 17012.2.4 Adhesives 17012.2.5 Integration Process Performance 17212.3 Conclusions 174References 17413 The 3MTM Wafer Support System (WSS) 175Blake Dronen and Richard Webb13.1 Introduction 17513.2 System Description 17513.3 General Advantages 17713.4 High-Temperature Material Solutions 17813.5 Process Considerations 18013.5.1 Wafer and Adhesive Delamination 18013.5.2 LTHC Glass Delamination 18113.6 Future Directions 18113.6.1 Thermal Stability 18113.6.2 Elimination of Adhesion Control Agents 18213.6.3 Laser-Free Release Layer 18313.7 Summary 183Reference 18414 Comparison of Temporary Bonding and Debonding Process Flows 185Matthew Lueck14.1 Introduction 18514.2 Studies of Wafer Bonding and Thinning 18614.3 Backside Processing 18614.4 Debonding and Cleaning 188References 18915 Thinning, Via Reveal, and Backside Processing – Overview 191Eric Beyne, Anne Jourdain, and Alain Phommahaxay15.1 Introduction 19115.2 Wafer Edge Trimming 19215.3 Thin Wafer Support Systems 19415.3.1 Glass Carrier Support System with Laser Debonding Approach 19615.3.2 Thermoplastic Glue Thin Wafer Support System – Thermal Slide Debondable System 19615.3.3 Room-Temperature, Peel-Debondable Thin Wafer Support Systems 19715.4 Wafer Thinning 19815.5 Thin Wafer Backside Processing 20215.5.1 Via-Middle Thin Wafer Backside Processing: “Via-Reveal” Process 20215.5.1.1 Mechanical Via Reveal 20215.5.1.2 “Soft” Via Reveal 20215.5.2 Via-Last Thin Wafer Backside Processing 203References 20516 Backside Thinning and Stress-Relief Techniques for Thin Silicon Wafers 207Christof Landesberger, Christoph Paschke, Hans-Peter Sp€ohrle, and Karlheinz Bock16.1 Introduction 20716.2 Thin Semiconductor Devices 20716.3 Wafer Thinning Techniques 20816.3.1 Wafer Grinding 20916.3.2 Wet-Chemical Spin Etching 21016.3.3 CMP Polishing 21116.3.4 Plasma Dry Etching 21216.3.5 Dry Polish 21316.3.6 Chemical–Mechanical Grinding (CMG) 21416.4 Fracture Tests for Thin Silicon Wafers 21416.5 Comparison of Stress-Relief Techniques for Wafer Backside Thinning 21616.6 Process Flow for Wafer Thinning and Dicing 22016.7 Summary and Outlook on 3D Integration 222References 22317 Via Reveal and Backside Processing 227Mitsumasa Koyanagi and Tetsu Tanaka17.1 Introduction 22717.2 Via Reveal and Backside Processing in Via-Middle Process 22717.3 Backside Processing in Back-Via Process 23217.4 Backside Processing and Impurity Gettering 23417.5 Backside Processing for RDL Formation 237References 23918 Dicing, Grinding, and Polishing (Kiru Kezuru and Migaku) 241Akihito Kawai18.1 Introduction 24118.2 Grinding and Polishing 24118.2.1 Grinding General 24118.2.1.1 Grinding Method 24118.2.1.2 Rough Grinding and Fine Grinding 24218.2.1.3 The Grinder Polisher 24318.2.2 Thinning 24318.2.2.1 Stress Relief 24518.2.2.2 Die Attach Film 24618.2.2.3 All-in-One System 24618.2.2.4 Dicing Before Grinding 24618.2.3 Grinding Topics for 3DIC Such as TSV Devices 24618.2.3.1 Wafer Support System 24618.2.3.2 Edge Trimming 24718.2.3.3 Grinding to Improve Flatness 24818.2.3.4 Higher Level of Cleanliness 24818.2.3.5 Via Reveal 24918.2.3.6 Planarization 24918.3 Dicing 25018.3.1 Blade Dicing General 25018.3.1.1 Dicing Method 25018.3.1.2 Blade Dicing Point 25018.3.1.3 Blade 25118.3.1.4 Optimization of Process Control 25218.3.1.5 Dicer 25218.3.1.6 Dual Dicing Applications 25218.3.2 Thin Wafer Dicing 25318.3.3 Low-k Dicing 25418.3.4 Other Laser Dicing 25418.3.4.1 Ablation 25418.3.4.2 Laser Full Cut Application 25518.3.4.3 Stealth Dicing (SD) 25618.3.5 Dicing Topics for 3D-IC Such as TSV 25718.3.5.1 Cutting of Chip on Chip (CoC) and Chip on Wafer (CoW) 25818.3.5.2 Singulation of CoW and Wafer on Wafer (WoW) 25918.4 Summary 260Further Reading 26019 Overview of Bonding and Assembly for 3D Integration 261James J.-Q. Lu, Dingyou Zhang, and Peter Ramm19.1 Introduction 26119.2 Direct, Indirect, and Hybrid Bonding 26219.3 Requirements for Bonding Process and Materials 26319.4 Bonding Quality Characterization 26719.5 Discussion of Specific Bonding and Assembly Technologies 26919.6 Summary and Conclusions 273References 27420 Bonding and Assembly at TSMC 279Douglas C.H. Yu20.1 Introduction 27920.2 Process Flow 28020.3 Chip-on-Wafer Stacking 28120.4 CoW-on-Substrate (CoWoS) Stacking 28320.5 CoWoS Versus CoCoS 28320.6 Testing and Known Good Stacks (KGS) 28420.7 Future Perspectives 285References 28521 TSV Packaging Development at STATS ChipPAC 287Rajendra D. Pendse21.1 Introduction 28721.2 Development of the 3DTSV Solution for Mobile Platforms 28921.3 Alternative Approaches and Future Developments 293References 29422 Cu–SiO2 Hybrid Bonding 295Léa Di Cioccio, S. Moreau, Loïc Sanchez, Floriane Baudin, Pierric Gueguen, Sebastien Mermoz, Yann Beilliard, and Rachid Taibi22.1 Introduction 29522.2 Blanket Cu–SiO2 Direct Bonding Principle 29622.2.1 Chemical–Mechanical Polishing Parameters 29622.3 Aligned Bonding 29922.3.1 Wafer-to-Wafer Bonding 29922.3.2 Die-to-Wafer Bonding in Pick-and-Place Equipment 29922.3.3 Die-to-Wafer by the Self-Assembly Technique 30022.4 Blanket Metal Direct Bonding Principle 30222.5 Electrical Characterization 30422.5.1 Wafer-to-Wafer and Die-to-Wafer Copper-Bonding Electrical Characterization 30422.5.2 Reliability 30722.5.3 Thermal Cycling 30722.5.4 Stress Voiding (SIV) Test on 200 °C Postbonding Annealed Samples 30822.5.5 Package-Level Electromigration Test 30922.6 Conclusions 310References 31123 Bump Interconnect for 2.5D and 3D Integration 313Alan Huffman23.1 History 31323.2 C4 Solder Bumps 31523.3 Copper Pillar Bumps 31623.4 Cu Bumps 31923.5 Electromigration 320References 32224 Self-Assembly Based 3D and Heterointegration 325Takafumi Fukushima and Jicheol Bea24.1 Introduction 32524.2 Self-Assembly Process 32524.3 Key Parameters of Self-Assembly on Alignment Accuracies 32724.4 How to Interconnect Self-Assembled Chips to Chips or Wafers 32824.4.1 Flip-Chip-to-Wafer 3D Integration 32924.4.2 Reconfigured-Wafer-to-Wafer 3D Integration 331References 33225 High-Accuracy Self-Alignment of Thin Silicon Dies on Plasma-Programmed Surfaces 335Christof Landesberger, Mitsuru Hiroshima, Josef Weber, and Karlheinz Bock25.1 Introduction 33525.2 Principle of Fluidic Self-Alignment Process for Thin Dies 33525.3 Plasma Programming of the Surface 33625.4 Preparation of Materials for Self-Alignment Experiments 33725.5 Self-Alignment Experiments 33825.6 Results of Self-Alignment Experiments 33925.7 Discussion 34125.8 Conclusions 342References 34326 Challenges in 3D Fabrication 345Douglas C.H. Yu26.1 Introduction 34526.2 High-Volume Manufacturing for 3D Integration 34626.3 Technology Challenges 34626.4 Front-Side and Backside Wafer Processes 34626.5 Bonding and Underfills 35026.6 Multitier Stacking 35226.7 Wafer Thinning and Thin Die and Wafer Handling 35326.8 Strata Packaging and Assembly 35626.9 Yield Management 35926.10 Reliability 36026.11 Cost Management 36226.12 Future Perspectives 362References 36427 Cu TSV Stress: Avoiding Cu Protrusion and Impact on Devices 365Eric Beyne, Joke De Messemaeker, and Wei Guo27.1 Introduction 36527.2 Cu Stress in TSV 36527.3 Mitigation of Cu Pumping 36827.4 Impact of TSVs on FEOL Devices 371References 37828 Implications of Stress/Strain and Metal Contamination on Thinned Die 379Kangwook Lee and Mariappan Murugesan28.1 Introduction 37928.2 Impacts of Cu Contamination on Device Reliabilities in Thinned 3DLSI 37928.3 Impacts of Local Stress and Strain on Device Reliabilities in Thinned 3DLSI 38628.3.1 Microbump-Induced Stresses in Stacked LSIs 38728.3.2 Microbump-Induced TMS in LSI 38828.3.3 Microbump-Induced LMS 389References 39129 Metrology Needs for 2.5D/3D Interconnects 393Victor H. Vartanian, Richard A. Allen, Larry Smith, Klaus Hummler, Steve Olson, and Brian Sapp29.1 Introduction: 2.5D and 3D Reference Flows 39329.2 TSV Formation 39429.2.1 TSV Etch Metrology 39529.2.2 Liner, Barrier, and Seed Metrology 39729.2.3 Copper Fill Metrology (TSV Voids) 39929.2.4 Cross-Sectional SEM (Focused Ion Beam Milling Sample Preparation) 40029.2.5 X-Ray Microscopy and CT Inspection 40029.2.6 Stress Metrology in Cu and Si 40229.3 MEOL Metrology 40429.3.1 Edge Trim Inspection 40529.3.2 Bond Voids and Bond Strength Metrology 40629.3.2.1 Acoustic Microscopy: Operation 40729.3.2.2 Acoustic Microscopy for Defect Inspection and Review 40729.3.2.3 Other Bond Void Detection Techniques 40829.3.3 Bond Strength Metrology 40929.3.4 Bonded Wafer Thickness, Bow, and Warp 41029.3.4.1 Chromatic White Light 41129.3.4.2 Infrared Interferometry 41229.3.4.3 White Light Interferometry (or Coherence Scanning Interferometry) 41429.3.4.4 Laser Profiling 41529.3.4.5 Capacitance Probes 41629.3.4.6 Differential Backpressure Metrology 41729.3.4.7 Acoustic Microscopy for Measuring Bonded Wafer Thickness 41729.3.5 TSV Reveal Metrology 41829.4 Assembly and Packaging Metrology 42029.4.1 Wafer-Level C4 Bump and Microbump Metrology and Inspection 42129.4.2 Package-Level Inspection: Scanning Acoustic Microscopy 42229.4.3 Package-Level Inspection: X-Rays 42429.5 Summary 426References 427Index 431