Dr. Vijay Nath received his bachelor's degree in Physics and master's degree in Electronics from DDU Gorakhpur University, India in 1998 and 2001. He received a PGDCN from MMM Engineering College Gorakhpur (Gold Medalist) in 1999. He received his Ph.D. in VLSI Design & Technology from Dr. RML Avadh University, Faizabad in association with CEERI- Pilani in 2008. He was a member of the faculty of the Department of Electronics, DDU Gorakhpur University, Gorakhpur (2002-2006). In 2006, he joined as a faculty member in the Department of Electronics and Communication Engineering, Birla Institute of Technology Mesra, Ranchi, India. Currently he is Professor In-charge of VLSI Design Lab & Embedded System Design Lab, Dept. of ECE, BIT Mesra, Ranchi.  His research interests include analog, digital, mixed CMOS VLSI circuits, low power VLSI circuits, ADC, DAC, PTAT, CMOS bandgap voltage reference, piezoresistive pressure sensors, double ring capacitive pressure sensors, MEMS sensors, signal-processing circuits, ASICs, embedded systems designs, smart cardiac pacemaker, and early stage cancer detection.  He has to his credit around 100 publications in international journals and conferences. He is a member of several reputed professional and academic bodies including IETE, ISVE, and IEEE.

• A Secure Three-Factor Remote User Authentication Scheme Using Elliptic Curve Cryptosystem.- Implementation of Fingerprint-Based Biometric System and Its Integration With Hrms Application At Rdcis, Sail.- Fabrication and Investigation of Low Voltage Programmable Flash Memory Gate Stac.- An Effective Method For Maintenance Scheduling of Vehicles Using Neural Network.- Universally Verifiable Certificateless Signcryption Scheme For Manet.- Impact of Sidewall Spacer Layers On The Analog/Rf Performance of Nanoscale Double-Gate Junctionless Transistors.- A Novel Data Encryption Approach In The Grid Structured Binary Image.- Analysis of Electromagnetic Wave Using Explicit FDTD in TM Mode with Extrapolation.- A Dea Based Evolutionary Computation Model For Stock Market Forecasting.- Electrical Equivalent Model For Gene Regulatory System.- Colour Image Segmentation Techniques: A Survey.- Wireless Image Sensor Networks: A Review.- Design of A Low Cost Heart Rate Monitoring System.- Design of Da Based Fir Filter Architectures Using Lut Reduction Techniques.- Fractional Delay Fir Filter Architecture Using Numeric Strength Reduction Techniques.- Lifetime Enhancement of Wsn Based On Modified Heterogeneous Leach Protocol.- Modeling and Investigation of Electrothermally Actuated Micro-Gripper.- An Ultra Low Power Internet Controlled Home Automation System.- Depth Averaged Velocity Distribution For Symmetrical and Asymmetrical Compound Channels.- A 0.533 Db Noise Figure, 7 Mw Narrowband  Low Noise Amplifier For Global Position System Application.- Design of Ultra Low Power Cmos Class E Power Amplifier.- Cryptic Mining For Automatic Variable Key Based Cryptosystem.- Single Mode Negative Dispersion Hexagonal Photonic Crystal Fiber.- Improved Clustering For Categorical Data With Genetic Algorithm.- Balanced Wrapper Design To Test The Embedded Core Partitioned Into Multiple Layer For 3d Soc Targeting Power and Number of TSVS.- Investigations On The Logic Performance of Hybrid Cmosfets Comprising P-Ge/ N-Ingaas Mosfets With  Barrier Layers.- Antenna Path Loss Propagation Model In The Dehradun Valley At 1800 Mhz In L- Band.- Reduction of Dark Current In Qwip.- Design of Circular Disc Monopole Antenna For Uwb Application.

Dr. Vijay Nath received his bachelor's degree in Physics and master's degree in Electronics from DDU Gorakhpur University, India in 1998 and 2001. He received a PGDCN from MMM Engineering College Gorakhpur (Gold Medalist) in 1999. He received his Ph.D. in VLSI Design & Technology from Dr. RML Avadh University, Faizabad in association with CEERI- Pilani in 2008. He was a member of the faculty of the Department of Electronics, DDU Gorakhpur University, Gorakhpur (2002-2006). In 2006, he joined as a faculty member in the Department of Electronics and Communication Engineering, Birla Institute of Technology Mesra, Ranchi, India. Currently he is Professor In-charge of VLSI Design Lab & Embedded System Design Lab, Dept. of ECE, BIT Mesra, Ranchi.  His research interests include analog, digital, mixed CMOS VLSI circuits, low power VLSI circuits, ADC, DAC, PTAT, CMOS bandgap voltage reference, piezoresistive pressure sensors, double ring capacitive pressure sensors, MEMS sensors, signal-processing circuits, ASICs, embedded systems designs, smart cardiac pacemaker, and early stage cancer detection.  He has to his credit around 100 publications in international journals and conferences. He is a member of several reputed professional and academic bodies including IETE, ISVE, and IEEE.

• A Secure Three-Factor Remote User Authentication Scheme Using Elliptic Curve Cryptosystem.- Implementation of Fingerprint-Based Biometric System and Its Integration With Hrms Application At Rdcis, Sail.- Fabrication and Investigation of Low Voltage Programmable Flash Memory Gate Stac.- An Effective Method For Maintenance Scheduling of Vehicles Using Neural Network.- Universally Verifiable Certificateless Signcryption Scheme For Manet.- Impact of Sidewall Spacer Layers On The Analog/Rf Performance of Nanoscale Double-Gate Junctionless Transistors.- A Novel Data Encryption Approach In The Grid Structured Binary Image.- Analysis of Electromagnetic Wave Using Explicit FDTD in TM Mode with Extrapolation.- A Dea Based Evolutionary Computation Model For Stock Market Forecasting.- Electrical Equivalent Model For Gene Regulatory System.- Colour Image Segmentation Techniques: A Survey.- Wireless Image Sensor Networks: A Review.- Design of A Low Cost Heart Rate Monitoring System.- Design of Da Based Fir Filter Architectures Using Lut Reduction Techniques.- Fractional Delay Fir Filter Architecture Using Numeric Strength Reduction Techniques.- Lifetime Enhancement of Wsn Based On Modified Heterogeneous Leach Protocol.- Modeling and Investigation of Electrothermally Actuated Micro-Gripper.- An Ultra Low Power Internet Controlled Home Automation System.- Depth Averaged Velocity Distribution For Symmetrical and Asymmetrical Compound Channels.- A 0.533 Db Noise Figure, 7 Mw Narrowband  Low Noise Amplifier For Global Position System Application.- Design of Ultra Low Power Cmos Class E Power Amplifier.- Cryptic Mining For Automatic Variable Key Based Cryptosystem.- Single Mode Negative Dispersion Hexagonal Photonic Crystal Fiber.- Improved Clustering For Categorical Data With Genetic Algorithm.- Balanced Wrapper Design To Test The Embedded Core Partitioned Into Multiple Layer For 3d Soc Targeting Power and Number of TSVS.- Investigations On The Logic Performance of Hybrid Cmosfets Comprising P-Ge/ N-Ingaas Mosfets With  Barrier Layers.- Antenna Path Loss Propagation Model In The Dehradun Valley At 1800 Mhz In L- Band.- Reduction of Dark Current In Qwip.- Design of Circular Disc Monopole Antenna For Uwb Application.

Dr. Vijay Nath received his bachelor's degree in Physics and master's degree in Electronics from DDU Gorakhpur University, India in 1998 and 2001. He received a PGDCN from MMM Engineering College Gorakhpur (Gold Medalist) in 1999. He received his Ph.D. in VLSI Design & Technology from Dr. RML Avadh University, Faizabad in association with CEERI- Pilani in 2008. He was a member of the faculty of the Department of Electronics, DDU Gorakhpur University, Gorakhpur (2002-2006). In 2006, he joined as a faculty member in the Department of Electronics and Communication Engineering, Birla Institute of Technology Mesra, Ranchi, India. Currently he is Professor In-charge of VLSI Design Lab & Embedded System Design Lab, Dept. of ECE, BIT Mesra, Ranchi.  His research interests include analog, digital, mixed CMOS VLSI circuits, low power VLSI circuits, ADC, DAC, PTAT, CMOS bandgap voltage reference, piezoresistive pressure sensors, double ring capacitive pressure sensors, MEMS sensors, signal-processing circuits, ASICs, embedded systems designs, smart cardiac pacemaker, and early stage cancer detection.  He has to his credit around 100 publications in international journals and conferences. He is a member of several reputed professional and academic bodies including IETE, ISVE, and IEEE.

• A Secure Three-Factor Remote User Authentication Scheme Using Elliptic Curve Cryptosystem.- Implementation of Fingerprint-Based Biometric System and Its Integration With Hrms Application At Rdcis, Sail.- Fabrication and Investigation of Low Voltage Programmable Flash Memory Gate Stac.- An Effective Method For Maintenance Scheduling of Vehicles Using Neural Network.- Universally Verifiable Certificateless Signcryption Scheme For Manet.- Impact of Sidewall Spacer Layers On The Analog/Rf Performance of Nanoscale Double-Gate Junctionless Transistors.- A Novel Data Encryption Approach In The Grid Structured Binary Image.- Analysis of Electromagnetic Wave Using Explicit FDTD in TM Mode with Extrapolation.- A Dea Based Evolutionary Computation Model For Stock Market Forecasting.- Electrical Equivalent Model For Gene Regulatory System.- Colour Image Segmentation Techniques: A Survey.- Wireless Image Sensor Networks: A Review.- Design of A Low Cost Heart Rate Monitoring System.- Design of Da Based Fir Filter Architectures Using Lut Reduction Techniques.- Fractional Delay Fir Filter Architecture Using Numeric Strength Reduction Techniques.- Lifetime Enhancement of Wsn Based On Modified Heterogeneous Leach Protocol.- Modeling and Investigation of Electrothermally Actuated Micro-Gripper.- An Ultra Low Power Internet Controlled Home Automation System.- Depth Averaged Velocity Distribution For Symmetrical and Asymmetrical Compound Channels.- A 0.533 Db Noise Figure, 7 Mw Narrowband  Low Noise Amplifier For Global Position System Application.- Design of Ultra Low Power Cmos Class E Power Amplifier.- Cryptic Mining For Automatic Variable Key Based Cryptosystem.- Single Mode Negative Dispersion Hexagonal Photonic Crystal Fiber.- Improved Clustering For Categorical Data With Genetic Algorithm.- Balanced Wrapper Design To Test The Embedded Core Partitioned Into Multiple Layer For 3d Soc Targeting Power and Number of TSVS.- Investigations On The Logic Performance of Hybrid Cmosfets Comprising P-Ge/ N-Ingaas Mosfets With  Barrier Layers.- Antenna Path Loss Propagation Model In The Dehradun Valley At 1800 Mhz In L- Band.- Reduction of Dark Current In Qwip.- Design of Circular Disc Monopole Antenna For Uwb Application.