Christophe Bobda – författare

"New Trends and Technologies in Computer-Aided Learning for Computer-Aided Design" contains the proceedings from the EduTech Workshop, an IFIP TC-10 Working Conference held in Perth, Australia. The workshop aimed to explore the interrelationship between computer-aided technology and computer-aided learning. Computation and communication technologies underpin work and development in many different areas. Among them, Computer-Aided Design of electronic systems and E-Learning technologies are two areas which are different but share many concerns. The design of CAD and E-Learning systems already touches on a number of parallels, such as system interoperability, user interfaces, standardization, EML-based formats, reusability aspects (of content or designs), and intellectual property rights. Furthermore, the teaching of Design Automation tools and methods is particularly amenable to a distant or blended learning setting, and implies the interconnection of typical CAD tools, such as simulators or synthesis tools, with e-learning tools.

Introduction in Reconfigurable Computing provides a comprehensive study of the field Reconfigurable Computing. It provides an entry point to the novice willing to move in the research field reconfigurable computing, FPGA and system on programmable chip design. The book can also be used as teaching reference for a graduate course in computer engineering, or as reference to advance electrical and computer engineers. It provides a very strong theoretical and practical background to the field of reconfigurable computing, from the early Estrin’s machine to the very modern architecture like coarse-grained reconfigurable device and the embedded logic devices. Apart from the introduction and the conclusion, the main chapter of the book are the following: Architecture of reconfigurable systems, which presents the technology and the architecture used in fined-grained and those used in coarse-grained reconfigurable devices.Design and implementation: This section deals with the implementation on reconfigurable system. It briefly covers the steps needed to implement application on today's FPGAs. And focus on the logic synthesis for FPGA, in particular LUT technology mapping.High-Level Synthesis for Reconfigurable Devices: The high-level synthesis for reconfigurable systems, also known as temporal partitioning is presented here. Several temporal partitioning techniques are presented and explained.Temporal placement: This section considers stand alone reconfigurable systems. Its assume that a kind of operating systems for reconfigurable systems is in charge of managing the resources of a given system and allocate space on a device for the computation of incoming tasks., and therefore presents several temporal placement approaches for off-line as well as on-line placement.On-line and Dynamic Interconnection: This chapter reviews andexplains the different approaches for allowing communication between modules dynamically placed at run-time on a given device. Designing a reconfigurable application on Xilinx Virtex FPGA: In this section, the different design approaches of partial reconfigurable systems on the Xilinx FPGAs that are one of the few one on the market with this feature, is explained.System on programmable chip: System on programmable chip is a hot topic in reconfigurable computing. This is mainly the integration of a system made upon some peripheral (UART, Ethernet, VGA, etc.), but also computational (Coding, filter, etc.) hardware modules on one programmable chip. The current usable solutions are presented: The book furthermore focusses on the development of adaptive multiprocessors on chip, i.e. systems consisting of a set of Processors and exchangeable hardware accelerators. Applications: This part covers the use of reconfigurable system in computer architecture (rapid prototyping, reconfigurable supercomputer, reconfigurable massively parallel computers) and algorithm better adapted for reconfigurable systems (distributed arithmetic, network packet processing, etc...)

Introduction in Reconfigurable Computing provides a comprehensive study of the field Reconfigurable Computing. It provides an entry point to the novice willing to move in the research field reconfigurable computing, FPGA and system on programmable chip design. The book can also be used as teaching reference for a graduate course in computer engineering, or as reference to advance electrical and computer engineers. It provides a very strong theoretical and practical background to the field of reconfigurable computing, from the early Estrin’s machine to the very modern architecture like coarse-grained reconfigurable device and the embedded logic devices. Apart from the introduction and the conclusion, the main chapter of the book are the following:

Architecture of reconfigurable systems, which presents the technology and the architecture used in fined-grained and those used in coarse-grained reconfigurable devices.

Design and implementation: This section deals with the implementation on reconfigurable system. It briefly covers the steps needed to implement application on today''s FPGAs. And focus on the logic synthesis for FPGA, in particular LUT technology mapping.

High-Level Synthesis for Reconfigurable Devices: The high-level synthesis for reconfigurable systems, also known as temporal partitioning is presented here. Several temporal partitioning techniques are presented and explained.

Temporal placement: This section considers stand alone reconfigurable systems. Its assume that a kind of operating systems for reconfigurable systems is in charge of managing the resources of a given system and allocate space on a device for the computation of incoming tasks., and therefore presents several temporal placement approaches for off-line as well as on-line placement.

On-line and Dynamic Interconnection: This chapter reviews andexplains the different approaches for allowing communication between modules dynamically placed at run-time on a given device.

Designing a reconfigurable application on Xilinx Virtex FPGA: In this section, the different design approaches of partial reconfigurable systems on the Xilinx FPGAs that are one of the few one on the market with this feature, is explained.

System on programmable chip: System on programmable chip is a hot topic in reconfigurable computing. This is mainly the integration of a system made upon some peripheral (UART, Ethernet, VGA, etc.), but also computational (Coding, filter, etc.) hardware modules on one programmable chip. The current usable solutions are presented: The book furthermore focusses on the development of adaptive multiprocessors on chip, i.e. systems consisting of a set of Processors and exchangeable hardware accelerators.

Applications: This part covers the use of reconfigurable system in computer architecture (rapid prototyping, reconfigurable supercomputer, reconfigurable massively parallel computers) and algorithm better adapted for reconfigurable systems (distributed arithmetic, network packet processing, etc...)

This publication addresses distributed embedded smart cameras –cameras that perform on board analysis and collaborate with other cameras. This book provides the material required to better understand the architectural design challenges of embedded smart camera systems, the hardware/software ecosystem, the design approach for and applications of distributed smart cameras together with the state-of-the-art algorithms. The authors concentrate on the architecture, hardware/software design, realization of smart camera networks from applications to architectures, in particular in the embedded and mobile domains.

This publication addresses distributed embedded smart cameras –cameras that perform on board analysis and collaborate with other cameras. This book provides the material required to better understand the architectural design challenges of embedded smart camera systems, the hardware/software ecosystem, the design approach for and applications of distributed smart cameras together with the state-of-the-art algorithms. The authors concentrate on the architecture, hardware/software design, realization of smart camera networks from applications to architectures, in particular in the embedded and mobile domains.

"New Trends and Technologies in Computer-Aided Learning for Computer-Aided Design" contains the proceedings from the EduTech Workshop, an IFIP TC-10 Working Conference held in Perth, Australia. The workshop aimed to explore the interrelationship between computer-aided technology and computer-aided learning. Computation and communication technologies underpin work and development in many different areas. Among them, Computer-Aided Design of electronic systems and E-Learning technologies are two areas which are different but share many concerns. The design of CAD and E-Learning systems already touches on a number of parallels, such as system interoperability, user interfaces, standardization, EML-based formats, reusability aspects (of content or designs), and intellectual property rights. Furthermore, the teaching of Design Automation tools and methods is particularly amenable to a distant or blended learning setting, and implies the interconnection of typical CAD tools, such as simulators or synthesis tools, with e-learning tools.

Introduction in Reconfigurable Computing provides a comprehensive study of the field Reconfigurable Computing. It provides an entry point to the novice willing to move in the research field reconfigurable computing, FPGA and system on programmable chip design. The book can also be used as teaching reference for a graduate course in computer engineering, or as reference to advance electrical and computer engineers. It provides a very strong theoretical and practical background to the field of reconfigurable computing, from the early Estrin’s machine to the very modern architecture like coarse-grained reconfigurable device and the embedded logic devices. Apart from the introduction and the conclusion, the main chapter of the book are the following: Architecture of reconfigurable systems, which presents the technology and the architecture used in fined-grained and those used in coarse-grained reconfigurable devices.Design and implementation: This section deals with the implementation on reconfigurable system. It briefly covers the steps needed to implement application on today's FPGAs. And focus on the logic synthesis for FPGA, in particular LUT technology mapping.High-Level Synthesis for Reconfigurable Devices: The high-level synthesis for reconfigurable systems, also known as temporal partitioning is presented here. Several temporal partitioning techniques are presented and explained.Temporal placement: This section considers stand alone reconfigurable systems. Its assume that a kind of operating systems for reconfigurable systems is in charge of managing the resources of a given system and allocate space on a device for the computation of incoming tasks., and therefore presents several temporal placement approaches for off-line as well as on-line placement.On-line and Dynamic Interconnection: This chapter reviews andexplains the different approaches for allowing communication between modules dynamically placed at run-time on a given device. Designing a reconfigurable application on Xilinx Virtex FPGA: In this section, the different design approaches of partial reconfigurable systems on the Xilinx FPGAs that are one of the few one on the market with this feature, is explained.System on programmable chip: System on programmable chip is a hot topic in reconfigurable computing. This is mainly the integration of a system made upon some peripheral (UART, Ethernet, VGA, etc.), but also computational (Coding, filter, etc.) hardware modules on one programmable chip. The current usable solutions are presented: The book furthermore focusses on the development of adaptive multiprocessors on chip, i.e. systems consisting of a set of Processors and exchangeable hardware accelerators. Applications: This part covers the use of reconfigurable system in computer architecture (rapid prototyping, reconfigurable supercomputer, reconfigurable massively parallel computers) and algorithm better adapted for reconfigurable systems (distributed arithmetic, network packet processing, etc...)