Jagana Bihari Padhy – författare

This book explores the synergy between very large-scale integration (VLSI) and machine learning (ML) and its applications across various domains. It investigates how ML techniques can enhance the design and testing of VLSI circuits, improve power efficiency, optimize layouts, and enable novel architectures.

This book bridges the gap between VLSI and ML, showcasing the potential of this integration in creating innovative electronic systems, advancing computing capabilities, and paving the way for a new era of intelligent devices and technologies. Additionally, it covers how VLSI technologies can accelerate ML algorithms, enabling more efficient and powerful data processing and inference engines. It explores both hardware and software aspects, covering topics like hardware accelerators, custom hardware for specific ML tasks, and ML-driven optimization techniques for chip design and testing.

This book will be helpful for academicians, researchers, postgraduate students, and those working in ML-driven VLSI.