Pinaki Mazumder – författare

Lectures on Digital Design Principles provides students an accessible reference for engaging with the building blocks of digital logic design. The book is an aggregation of lectures for an introductory course and provides a conversational style to better engage with students. Since the text is developed from lectures, important and foundational concepts are highlighted without tedious proofs. With respect to subject matter, students are introduced to different methods of abstracting digital systems, along with the strengths and weaknesses of these different methods. For example, Boolean logic can be represented as algebraic equations, gate level diagrams, switching circuits, truth tables, etc. Strengths and drawbacks to these representations are discussed in the context of Boolean minimization and electronic design automation. The text also delves into dynamic behavior of digital circuits with respect to timing in combinational circuits and state transitions in sequential circuits.

Lectures on Digital Design Principles provides students an accessible reference for engaging with the building blocks of digital logic design. The book is an aggregation of lectures for an introductory course and provides a conversational style to better engage with students. Since the text is developed from lectures, important and foundational concepts are highlighted without tedious proofs. With respect to subject matter, students are introduced to different methods of abstracting digital systems, along with the strengths and weaknesses of these different methods. For example, Boolean logic can be represented as algebraic equations, gate level diagrams, switching circuits, truth tables, etc. Strengths and drawbacks to these representations are discussed in the context of Boolean minimization and electronic design automation. The text also delves into dynamic behavior of digital circuits with respect to timing in combinational circuits and state transitions in sequential circuits.

Explains current co-design and co-optimization methodologies for building hardware neural networks and algorithms for machine learning applications 

This book focuses on how to build energy-efficient hardware for neural networks with learning capabilities—and provides co-design and co-optimization methodologies for building hardware neural networks that can learn. Presenting a complete picture from high-level algorithm to low-level implementation details, Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design also covers many fundamentals and essentials in neural networks (e.g., deep learning), as well as hardware implementation of neural networks.

The book begins with an overview of neural networks. It then discusses algorithms for utilizing and training rate-based artificial neural networks. Next comes an introduction to various options for executing neural networks, ranging from general-purpose processors to specialized hardware, from digital accelerator to analog accelerator. A design example on building energy-efficient accelerator for adaptive dynamic programming with neural networks is also presented. An examination of fundamental concepts and popular learning algorithms for spiking neural networks follows that, along with a look at the hardware for spiking neural networks. Then comes a chapter offering readers three design examples (two of which are based on conventional CMOS, and one on emerging nanotechnology) to implement the learning algorithm found in the previous chapter. The book concludes with an outlook on the future of neural network hardware.

Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design is an ideal resource for researchers, scientists, software engineers, and hardware engineers dealing with the ever-increasing requirement on power consumption and response time. It is also excellent for teaching and training undergraduate and graduate students about the latest generation neural networks with powerful learning capabilities. 

Explains current co-design and co-optimization methodologies for building hardware neural networks and algorithms for machine learning applications 

This book focuses on how to build energy-efficient hardware for neural networks with learning capabilities—and provides co-design and co-optimization methodologies for building hardware neural networks that can learn. Presenting a complete picture from high-level algorithm to low-level implementation details, Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design also covers many fundamentals and essentials in neural networks (e.g., deep learning), as well as hardware implementation of neural networks.

The book begins with an overview of neural networks. It then discusses algorithms for utilizing and training rate-based artificial neural networks. Next comes an introduction to various options for executing neural networks, ranging from general-purpose processors to specialized hardware, from digital accelerator to analog accelerator. A design example on building energy-efficient accelerator for adaptive dynamic programming with neural networks is also presented. An examination of fundamental concepts and popular learning algorithms for spiking neural networks follows that, along with a look at the hardware for spiking neural networks. Then comes a chapter offering readers three design examples (two of which are based on conventional CMOS, and one on emerging nanotechnology) to implement the learning algorithm found in the previous chapter. The book concludes with an outlook on the future of neural network hardware.

Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design is an ideal resource for researchers, scientists, software engineers, and hardware engineers dealing with the ever-increasing requirement on power consumption and response time. It is also excellent for teaching and training undergraduate and graduate students about the latest generation neural networks with powerful learning capabilities. 

Build the microchips of the future with this revolutionary new information transfer technology

Advancements in high-performance computing have continually demanded for progress in disruptive technological research and innovations. Moore’s Law has pushed the Very Large Scale Integration (VLSI) technology to pack MOS devices inside a chip at an exponential rate, thereby surpassing now eight billion transistors per cm2. This has concomitantly fueled the growth of multilayered on-chip interconnects comprising metallic and low dielectric materials.

Artificial Plasmonics for VLSI Interconnects introduces a new method for improving chip performance by harnessing the power of information transfer among chips at terahertz frequency. This revolutionary new electromagnetic wave engineering, called a spoof surface plasmon polariton, adapts the principles of VLSI and terahertz interconnect technology along with the artificial plasmonics to transfer huge quantities of data at vastly improved speeds. It constitutes a potentially decisive contribution to the pursuit of faster and more capacious VLSI chips.

In Artificial Plasmonics for VLSI Interconnects, readers will also find:

Artificial Plasmonics for VLSI Interconnects is ideal for engineers, researchers, and scientists working in electronics, electromagnetics, and optics.

This book delves into a wide array of topics, ranging from memristor and its emulator to chaotic circuits based on memristor, memristor-based en/decryption systems, filter design based on memristive family, memristive filter for signal processing, memristor network-based swarm intelligence, dynamic analysis of memristive neural networks, and the application of memristor-based neural networks. It provides a comprehensive and systematic exploration of how memristors empower and drive cutting-edge research in neuromorphic computing and artificial intelligence. This book encourages fostering interdisciplinary information literacy and cultivating cross-disciplinary computational thinking. This book plays a pivotal role in embracing and advancing the development of neuromorphic computing. Through profound foundational theories and academic analysis methods, this book guides artificial intelligence graduate students and engineering professionals in constructing a comprehensive knowledge and technological framework for memristor research.