Cross-Layer Reliability of Computing Systems

Inbunden, Engelska, 2020

Del i serien Materials, Circuits and Devices

1 729 kr

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Beskrivning

Reliability has always been a major concern in designing computing systems. However, the increasing complexity of such systems has led to a situation where efforts for assuring reliability have become extremely costly, both for the design of solutions for the mitigation of possible faults, and for the reliability assessment of such techniques.Cross-layer reliability is fast becoming the preferred solution. In a cross-layer resilient system, physical and circuit level techniques can mitigate low-level faults. Hardware redundancy can be used to manage errors at the hardware architecture layer. Eventually, software implemented error detection and correction mechanisms can manage those errors that escaped the lower layers of the stack.This book presents state-of-the-art solutions for increasing the resilience of computing systems, both at single levels of abstraction and multi-layers. The book begins by addressing design techniques to improve the resilience of computing systems, covering the logic layer, the architectural layer and the software layer. The second part of the book focuses on cross-layer resilience, including coverage of physical stress, reliability assessment approaches, fault injection at the ISA level, analytical modelling for cross-later resiliency, and stochastic methods.Cross-Layer Reliability of Computing Systems is a valuable resource for researchers, postgraduate students and professional computer architects focusing on the dependability of computing systems.

Produktinformation

Utgivningsdatum:2020-10-22
Mått:156 x 234 x 20 mm
Vikt:703 g
Format:Inbunden
Språk:Engelska
Serie:Materials, Circuits and Devices
Antal sidor:328
Förlag:Institution of Engineering and Technology
ISBN:9781785617973

Utforska kategorier

Elektronik och kommunikationer inom Naturvetenskap och teknik

Mer om författaren

Giorgio Di Natale is director of research for the National Research Center of France at the TIMA laboratory in Grenoble, France. His research interests include hardware security and trust, reliability, fault tolerance, and testing. He is the chair of the TTTC (Computer Society), Golden Core member of the Computer Society and Senior member of the IEEE.Dimitris Gizopoulos is a professor in the Department of Informatics & Telecommunications at the National and Kapodistrian University of Athens, Greece, where he leads the Computer Architecture Laboratory. His research focuses on the dependability, performance and energy efficiency of computing systems architectures built around general purpose microprocessors and specialized accelerators. He is a Fellow of IEEE and a Senior Member of ACM.Stefano Di Carlo is a tenured associate professor at Politecnico di Torino, Italy. His research interests include DFT, BIST, and dependability. He has published more than 170 papers in peer reviewed IEEE and ACM journals and conferences.Alberto Bosio is a full professor at Ecole Centrale de Lyon - INL in France. His research interests include approximate computing, in-memory computing, test and diagnosis of digital circuits and systems and reliability.Ramon Canal is an associate professor and the vice dean of postgraduate studies at the Facultat d'Informatica de Barcelona at the Universitat Politecnica de Catalunya-Barcelona Tech (UPC). He is currently working in the Computer Architecture Department in the VirtuOS (Virtualization and Operating Systems) group.

Innehållsförteckning

Part I: Design techniques to improve the resilience of computing systemsChapter 1: Technological layerChapter 2: Design techniques to improve the resilience of computing systems: logic layerChapter 3: Design techniques to improve the resilience of computing systems: architectural layerChapter 4: Design techniques to improve the resilience of computing systems: software layerChapter 5: Cross-layer resilience Part II: Reliability assessmentChapter 6: Physical stressChapter 7: Soft error modeling and simulationChapter 8: Microarchitecture-level reliability assessment of multi-core processorsChapter 9: Fault injection at the instruction set architecture (ISA) levelChapter 10: Analytical modeling for crosslayer resiliencyChapter 11: Stochastic methods