Applied Reconfigurable Computing. Architectures, Tools, and Applications

21st International Symposium, ARC 2025, Seville, Spain, April 9–11, 2025, Proceedings

AvRoberto Giorgi,Mirjana Stojilović

Häftad, Engelska, 2025

Del 15594 i serien Lecture Notes in Computer Science

828 kr

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Beskrivning

Architectures, Tools, and Applications, ARC 2025, held in Seville, Spain, during April 9–11, 2025. mso-ansi-language: EN-US;">ARC 2025 covers a wide range of topics, including hardware acceleration, security and fault tolerance, energy-efficient architectures, and emerging applications in artificial intelligence and high-performance computing.

Produktinformation

Utgivningsdatum:2025-04-04
Mått:155 x 235 x 15 mm
Vikt:400 g
Format:Häftad
Språk:Engelska
Serie:Lecture Notes in Computer Science
Antal sidor:246
Förlag:Springer International Publishing AG
ISBN:9783031879944

Utforska kategorier

Programvaruutveckling inom Data och IT
Hårdvara inom Data och IT

Innehållsförteckning

First Twenty Years of the International Symposium on Applied Reconfigurable Computing (ARC): a Selection of Papers.- HT-NoC: Reconfigurable High Throughput Network-on-Chip for AI Dataflow Accelerators.- An MLIR-based Compilation Framework for CGRA Application Deployment.- Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA.- RePAIR: Reconfigurable Platform for AI Resilience within RISC-V Ecosystem.- ROBoost: A Study of FPGA Logic-Based Power-Wasting Primitives.- FLARE: An FPGA-based Universal Large Flow Detection Engine.- Out-of-the-Box Performance of FPGAs for ML Workloads using Vitis AI.- A Heterogeneous Embedded Platform for AI-based Protocol Identification.- Counting Heavy Items in Filtered Data Streams Using an HLS-Generated FPGA Kernel.- Ultra-low Latency and Extreme Throughput Echo State Neural Networks on FPGA.- A Reconfigurable Stream-Based FPGA Accelerator for Bayesian Confidence Propagation Neural Networks.- Real-Time Multi-Object Tracking using YOLOv8 and SORT on a SoC FPGA.- Dynamic Function Exchange in FPGA to Redefine RISC-V Multicore Architectures at Runtime.