Georges Gielen – författare

Modern system-on-chip designs are increasingly mixed-signal designs that require efficient systematic design methodologies and supporting computer-aided design (CAD) tools to manage the design complexity in the available design time, that is ever decreasing due to tightening time-to-market constraints. The purpose of this work is to provide an overview of research results that have been achieved as part of the Low-Power Initiative of the European Union, in the field of analog, RF and mixed-signal design methodologies and CAD tools. It is a representative sampling of the state-of-the art in this area, with special focus on low-power design methodologies and tools for analog and RF circuits and architectures. Concrete designs, mainly for telecommunication applications, such as low-noise amplifiers, oscillators, filters, but also complete transceiver front-ends, are discussed and analyzed in a methodological way, and their modeling and simulation, both at the circuit level and at the architectural level, are treated.In this way, the eleven contributions of this book combine in a unique way designs with methodologies and CAD that should be interesting to designers and CAD developers, both in industry and academia.

This work addresses the design methodologies and CAD tools that are available for the systematic design and design automation of analogue integrated circuits. Two complementary approaches are discussed. In the first part the AMGIE analogue synthesis system is described. AMGIE is the first analogue synthesis system that automates the full design process from specifications down to verified layout. It is targeted to the design of moderate-complexity circuits. It relies on design and circuit knowledge stored in the tool's libraries and can be used by both novice and experienced analogue designers as well as system-level designers. The inner workings are explained in detail, with (practical) examples to demonstrate how the implemented algorithms and techniques work. Experimental results obtained with the AMGIE system are reported, including actual fabricated and measured circuits. The second approach, that is, the systematic design of high-performance analog circuits, is discussed in the second part of the book. This approach is supported by tools to boost the productivity of the designer.An example of such a tool is Mondriaan, that is targeted towards the automatic layout generation of highly regular analog blocks. The proposed systematic design methodology is then applied to the design of high-accuracy current-steering digital to analog converters (DACs). The full design path is discussed in detail. By using the Mondriaan tool and other in-house developed and commercially available tools, the first 14-bit accurate current-steering DAC without tuning or trimming in CMOS technology has been fabricated and measured. Both complementary approaches increase analog design productivity. Design times of the different design experiments undertaken are reported throughout the book to demonstrate this.

Analog integrated circuits are very important as interfaces between the digital parts of integrated electronic systems and the outside world. A large portion of the effort involved in designing these circuits is spent in the layout phase. Whereas the physical design of digital circuits is automated to a large extent, the layout of analog circuits is still a manual, time-consuming and error-prone task. This is mainly due to the continuous nature of analog signals, which causes analog circuit performance to be very sensitive to layout parasitics. The parasitic elements associated with interconnect wires cause loading and coupling effects that degrade the frequency behaviour and the noise performance of analog circuits. Device mismatch and thermal effects put a fundamental limit on the achievable accuracy of circuits. For successful automation of analog layout, advanced place and route tools that can handle these critical parasitics are required. In the past, automatic analog layout tools tried to optimize the layout without quantifying the performance degradation introduced by layout parasitics.Therefore, it was not guaranteed that the resulting layout met the specifications and one or more layout iterations could be needed. The authors propose a performance-driven layout strategy to overcome this problem. In this methodology, the layout tools are driven by performance constraints, such that the final layout, with parasitic effects, still satisfies the specifications of the circuit. The performance degradation associated with an intermediate layout solution is evaluated at runtime using predetermined sensitivities. In contrast with other performance-driven layout methodologies, the tools proposed in this book operate directly on the performance constraints, without an intermediate parasitic constraint generation step. Besides its influence on the performance, layout also has a profound impact on the yield and testability of an analog circuit. The authors outline a new criterion to quantify the detectability of a fault and combine this with a yield model to evaluate the testability of an integrated circuit layout.They then integrate this technique with their performance-driven routing algorithm to produce layouts that have optimal manufacturability while still meeting their performance specifications.

It is a great honor to provide a few words of introduction for Dr. Georges Gielen's and Prof. Willy Sansen's book "Symbolic analysis for automated design of analog integrated circuits". The symbolic analysis method presented in this book represents a significant step forward in the area of analog circuit design. As demonstrated in this book, symbolic analysis opens up new possibilities for the development of computer-aided design (CAD) tools that can analyze an analog circuit topology and automatically size the components for a given set of specifications. Symbolic analysis even has the potential to improve the training of young analog circuit designers and to guide more experienced designers through second-order phenomena such as distortion. This book can also serve as an excellent reference for researchers in the analog circuit design area and creators of CAD tools, as it provides a comprehensive overview and comparison of various approaches for analog circuit design automation and an extensive bibliography. The world is essentially analog in nature, hence most electronic systems involve both analog and digital circuitry. As the number of transistors that can be integrated on a single integrated circuit (IC) substrate steadily increases over time, an ever increasing number of systems will be implemented with one, or a few, very complex ICs because of their lower production costs.

This book brings together important contributions and state-of-the-art research results in the rapidly advancing area of symbolic analysis of analog circuits. It is also of interest to those working in analog CAD. The book is an excellent reference, providing insights into some of the most important issues in the symbolic analysis of analog circuits.

nalog circuits are fascinating artifacts. They manipulate signals whose informa- Ationcontentisrichcomparedtodigitalsignalsthatcarryminimalamountofinf- mation;theyaredelicateinthatanyperturbationduetoparasiticelements,todelays,to interactionswithotherelementsandwiththeenvironmentmaycauseasigni?cantloss ofinformation. Thedif?cultyindealingwiththeseartifactsistoprotectthemfromall possibleattacks, evenminorones, fromthephysicalworld. Theironyisthattheyare oftenusedtofunnelinformationfromandtothephysicalworldtoandfromtheabstr- tionofthedigitalworldandforthisfunction, theyareirreplaceable. Nowonderthen that analog designers form a club of extraordinary gentlemen where art (or magic?) ratherthanscienceisthesharedtrade. Theyaredif?culttotrainsinceexperienceand intuitionarethetraitsthat characterize them. Andthey have dif?cultiesinexplaining what is the process they use to reach satisfactory results. Tools used for design (s- ulation) are mainly replacing the test benches of an experimental lab.However, the growing complexity of the integrated systems being designed today together with the increasing fragility of analog components brought about by shrinking geometries and reducedpowerconsumptionisposingseverechallengestotraditionalanalogdesigners to produce satisfactory results in a short time. At the same time, the need for expe- enced analog designers has increased constantly since almost all designs, because of integration,docontainanalogcomponents. Thissituationhascreatedastronginterest in developing design methodologies and supporting tools that are based on rigorous, mathematically literate, approaches. Doing so will make it possible to leverage the expertiseofseasonedanalogdesignersandtotrainnewgenerationsfasterandbetter. Inthepast, severalattemptshavebeenmadeinacademia andindustrytocreatethese methodologies and to extend the set of tools available. They have had questionable acceptance in the analog design community. However, recently, a ?urry of start-ups andincreasedinvestmentbyEDAcompaniesinnoveltoolssignalasigni?cantchange inmarketattentiontotheanalogdomain. Ipersonallybelievethattosubstantially- prove quality and design time, tools are simply insuf?cient.A design methodology based on a hierarchy of abstraction layers, successive re?nement between two ad- cent layers, and extensive veri?cation at every layer is necessary. To do so, we need to build theories and models that have strong mathematical foundations. The analog design technology community is as strong as it has ever been.

As the miniaturization of semiconductor technology continues, electronic s- tems on chips o?er a more extensive and more complex functionality with better performance, higher frequencies and less power consumption. Whereas digital designers can take full advantage of the availability of design auto- tiontoolstobuildhugesystems,thelackofsupportbycomputerprogramsfor di?erent abstraction levels makes analog design a time-consuming handcraft which limits the possibilities to implement large systems. Various approaches for?ndingoptimalvaluesfortheparametersofanalogcells,likeopamps,have been investigated since the mid-1980s, and they have made their entrance in commercial applications. However, a larger impact on the performance is - pected if tools are developed which operate on a higher abstraction level and consider multiple architectural choices to realize a particular functionality. In this book, the opportunities, conditions, problems, solutions and systematic methodologies for this new generation of analog CAD tools are examined. Theoutlineofthisbookisasfollows. Inthe?rstpart,thecharacteristicsof the analog design process are systematically analyzed and several approaches for automated analog synthesis are summarized. Comparison of their prop- ties with the requirements for high-level synthesis of analog and mixed-signal systems results in a new design paradigm: the high-level design ?ow based on generic behavior. This design approach involves a modeling strategy using generic behavioral models and a synthesis strategy leading to the exploration of a heterogeneous design space containing di?erent architectures. The modeling strategy is further elaborated in Part II.

Driven by applications such as telecommunications, computing and consumer/multimedia and facilitated by the progress in CMOS ULSI technology, the microelectronics IC market is characterized by an ever-increasing level of integration complexity. Complete systems, that previously occupied one or more boards, are integrated on a few chips or even on one single multi-million transistor chip - a so called System-on-Chip (SoC). Although most functions in such integrated systems are implemented with digital or digital signal processing circuitry, the analogue circuits needed at the interface between the electronic system and the continuous-valued outside world are also being integrated on the same die for reasons of cost and performance. Unfortunately, the integration of both analogue and RF circuits and digital circuits on the same die not only offers many benefits, but also creates some technical difficulties. Since the analogue circuits exploit the low-level physics of the fabrication process, they remain difficult and costly to design, but they are also vulnerable to any kind of noise or crosstalk signals.The higher levels of integration (moving towards 100 million transistors per chip clocked at ever higher frequencies) make the mixed-signal signal integrity problem increasingly challenging. One of the most important problems is the parasitic supply and substrate noise coupling, caused by the fast switching of the digital circuitry that then propagates to the sensitive analogue circuitry via the common substrate. It is therefore important to be able to predict the impact of digital switching noise on the analogue circuit performance at the design stage of the integrated system, before the chip is taped out for fabrication, and to understand how this problem can be reduced. This text provides an overview of state-of-the-art research results in the field of substrate noise analysis and reduction techniques. Much of the reported work has been established as part of the Mixed-Signal Initiative of the European Union.

The ever-decreasing feature size has continuously provided improved functionality at a reduced cost. As the feature size decreased, designs moved from digital microprocessors and application specific integrated circuits (ASICs) to systems-on-a-chip (SoC). The design capabilities of the designer however, have not been increased equally. Analog design tools are only just emerging, and the design of the small analog part in the hostile digital environment, has become a tremendous bottleneck. This text introduces a design methodology that can help to bridge the productivity gap. Two different types of designs, depending on the design challenge, have been identified: commodity IP and star IP. Each category requires a different approach to boost design productivity. Commodity IP blocks are well suited to be automated in an analog synthesis environment and provided as soft IP. The design knowledge is usually common knowledge, and reuse is high accounting for the setup time needed for the analog library.Star IP still changes as technology evolves and the design cost can only be reduced by following a systematic design approach supported by point tools to relieve the designer from error-prone, repetitive tasks, allowing him/her to focus on new ideas to push the limits of the design. To validate the presented methodologies, three different industrial-strength applications have been selected and designed accordingly. Firstly, a particle detector front-end for space applications has been designed and embedded in the AMGIE library for further re-use. Performance compares favourably to an earlier manual design. Starting from specification, a physical layout can be generated within a few days. Secondly, current-steering D/A converters have been selected as a test-engine for the design methodology of Star IP. A novel topology has been developed allowing full flexibility to the designer in terms of switching scheme. This allows the designer to implement the Q2 Random Walk switching scheme which averages out random and systematic errors resulting in the first intrinsic 14-bit linear D/A converter in CMOS technology. The overall design time was reduced from 11 to four weeks.A third and final test-case, an 8 bit 200MS/s interpolating/averaging A/D converter has been designed. Performance and design times compare favorably to an earlier manual design. All experiments prove that despite general disbelieve, design cost can be reduced considerably, without compromising performance, by adopting the proper design methodology.

Analog integrated circuits are very important as interfaces between the digital parts of integrated electronic systems and the outside world. A large portion of the effort involved in designing these circuits is spent in the layout phase. Whereas the physical design of digital circuits is automated to a large extent, the layout of analog circuits is still a manual, time-consuming and error-prone task. This is mainly due to the continuous nature of analog signals, which causes analog circuit performance to be very sensitive to layout parasitics. The parasitic elements associated with interconnect wires cause loading and coupling effects that degrade the frequency behaviour and the noise performance of analog circuits. Device mismatch and thermal effects put a fundamental limit on the achievable accuracy of circuits. For successful automation of analog layout, advanced place and route tools that can handle these critical parasitics are required. In the past, automatic analog layout tools tried to optimize the layout without quantifying the performance degradation introduced by layout parasitics.Therefore, it was not guaranteed that the resulting layout met the specifications and one or more layout iterations could be needed. In Analog Layout Generation for Performance and Manufacturability, the authors propose a performance driven layout strategy to overcome this problem. In this methodology, the layout tools are driven by performance constraints, such that the final layout, with parasitic effects, still satisfies the specifications of the circuit. The performance degradation associated with an intermediate layout solution is evaluated at runtime using predetermined sensitivities. In contrast with other performance driven layout methodologies, the tools proposed in this book operate directly on the performance constraints, without an intermediate parasitic constraint generation step. This approach makes a complete and sensible trade-off between the different layout alternatives possible at runtime and therefore eliminates the possible feedback route between constraint derivation, placement and layout extraction. Besides its influence on the performance, layout also has a profound impact on the yield and testability of an analog circuit.In Analog Layout Generation for Performance and Manufacturability, the authors outline a new criterion to quantify the detectability of a fault and combine this with a yield model to evaluate the testability of an integrated circuit layout. They then integrate this technique with their performance driven routing algorithm to produce layouts that have optimal manufacturability while still meeting their performance specifications. Analog Layout Generation for Performance and Manufacturability will be of interest to analog engineers, researchers and students.

nalog circuits are fascinating artifacts. They manipulate signals whose informa- Ationcontentisrichcomparedtodigitalsignalsthatcarryminimalamountofinf- mation;theyaredelicateinthatanyperturbationduetoparasiticelements,todelays,to interactionswithotherelementsandwiththeenvironmentmaycauseasigni?cantloss ofinformation. Thedif?cultyindealingwiththeseartifactsistoprotectthemfromall possibleattacks, evenminorones, fromthephysicalworld. Theironyisthattheyare oftenusedtofunnelinformationfromandtothephysicalworldtoandfromtheabstr- tionofthedigitalworldandforthisfunction, theyareirreplaceable. Nowonderthen that analog designers form a club of extraordinary gentlemen where art (or magic?) ratherthanscienceisthesharedtrade. Theyaredif?culttotrainsinceexperienceand intuitionarethetraitsthat characterize them. Andthey have dif?cultiesinexplaining what is the process they use to reach satisfactory results. Tools used for design (s- ulation) are mainly replacing the test benches of an experimental lab.However, the growing complexity of the integrated systems being designed today together with the increasing fragility of analog components brought about by shrinking geometries and reducedpowerconsumptionisposingseverechallengestotraditionalanalogdesigners to produce satisfactory results in a short time. At the same time, the need for expe- enced analog designers has increased constantly since almost all designs, because of integration,docontainanalogcomponents. Thissituationhascreatedastronginterest in developing design methodologies and supporting tools that are based on rigorous, mathematically literate, approaches. Doing so will make it possible to leverage the expertiseofseasonedanalogdesignersandtotrainnewgenerationsfasterandbetter. Inthepast, severalattemptshavebeenmadeinacademia andindustrytocreatethese methodologies and to extend the set of tools available. They have had questionable acceptance in the analog design community. However, recently, a ?urry of start-ups andincreasedinvestmentbyEDAcompaniesinnoveltoolssignalasigni?cantchange inmarketattentiontotheanalogdomain. Ipersonallybelievethattosubstantially- prove quality and design time, tools are simply insuf?cient.A design methodology based on a hierarchy of abstraction layers, successive re?nement between two ad- cent layers, and extensive veri?cation at every layer is necessary. To do so, we need to build theories and models that have strong mathematical foundations. The analog design technology community is as strong as it has ever been.

The purpose of Substrate Noise Coupling in Mixed-Signal ASICs is to provide an overview of very recent research results in the field of substrate noise analysis and reduction techniques. Much of the reported work has been established as part of the Mixed-Signal Initiative of the European Union. It is a representative sampling of the current state of the art in this area. All the different aspects of the substrate noise coupling problem are covered. Some chapters describe techniques to model and reduce the digital switching noise injected in the substrate. Other chapters describe methods to analyse the propagation of the noise from the source (the digital circuitry) to the reception point (the embedded analog circuitry) through the substrate considered as a resistive/capacitive mesh. Finally, the remaining chapters describe techniques to model and especially to reduce the impact of substrate noise on the analog side. This is illustrated with several practical design examples and measurement results.

Systematic Design of Analog IP Blocks introduces a design methodology that can help to bridge the productivity gap. Two different types of designs, depending on the design challenge, have been identified: commodity IP and star IP. Each category requires a different approach to boost design productivity. Commodity IP blocks are well suited to be automated in an analog synthesis environment and provided as soft IP. The design knowledge is usually common knowledge, and reuse is high accounting for the setup time needed for the analog library. Star IP still changes as technology evolves and the design cost can only be reduced by following a systematic design approach supported by point tools to relieve the designer from error-prone, repetitive tasks, allowing him/her to focus on new ideas to push the limits of the design. To validate the presented methodologies, three different industrial-strength applications have been selected and designed accordingly.

This book brings together important contributions and state-of-the-art research results in the rapidly advancing area of symbolic analysis of analog circuits. It is also of interest to those working in analog CAD. The book is an excellent reference, providing insights into some of the most important issues in the symbolic analysis of analog circuits.

It is a great honor to provide a few words of introduction for Dr. Georges Gielen's and Prof. Willy Sansen's book "Symbolic analysis for automated design of analog integrated circuits". The symbolic analysis method presented in this book represents a significant step forward in the area of analog circuit design. As demonstrated in this book, symbolic analysis opens up new possibilities for the development of computer-aided design (CAD) tools that can analyze an analog circuit topology and automatically size the components for a given set of specifications. Symbolic analysis even has the potential to improve the training of young analog circuit designers and to guide more experienced designers through second-order phenomena such as distortion. This book can also serve as an excellent reference for researchers in the analog circuit design area and creators of CAD tools, as it provides a comprehensive overview and comparison of various approaches for analog circuit design automation and an extensive bibliography. The world is essentially analog in nature, hence most electronic systems involve both analog and digital circuitry. As the number of transistors that can be integrated on a single integrated circuit (IC) substrate steadily increases over time, an ever increasing number of systems will be implemented with one, or a few, very complex ICs because of their lower production costs.

This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed. The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.

In the first part the AMGIE analog synthesis system is described. AMGIE is the first analog synthesis system that automates the full design process from specifications down to verified layout. It is targeted to the design of moderate-complexity circuits. It relies on design and circuit knowledge stored in the tool's libraries and can be used by both novice and experienced analog designers as well as system-level designers. The inner workings are explained in detail, with (practical) examples to demonstrate how the implemented algorithms and techniques work. Experimental results obtained with the AMGIE system are reported, including actual fabricated and measured circuits. The second approach, i.e. the systematic design of high-performance analog circuits, is discussed in the second part of the book. This approach is supported by tools to boost the productivity of the designer. An example of such a tool is Mondriaan, that is targeted towards the automatic layout generation of highly regular analog blocks. The proposed systematic design methodology is then applied to the design of high-accuracy current-steering digital to analog converters (DACs). The full design path is discussed in detail. Both complementary approaches increase analog design productivity. Design times of the different design experiments undertaken are reported throughout the book to demonstrate this.

Modern System-on-Chip designs are increasingly mixed-signal designs that require efficient systematic design methodologies and supporting computer-aided design (CAD) tools to manage the design complexity in the available design time, that is ever decreasing due to tightening time-to-market constraints. The purpose of Low-Power Design Techniques and CAD Tools for Analog and RF Integrated Circuits is to provide an overview of very recent research results that have been achieved as part of the Low-Power Initiative of the European Union, in the field of analog, RF and mixed-signal design methodologies and CAD tools. It is a representative sampling of the current state of the art in this area, with special focus on low-power design methodologies and tools for analog and RF circuits and architectures. Concrete designs, mainly for telecommunication applications, such as low-noise amplifiers, oscillators, filters, but also complete transceiver front-ends, are discussed and analyzed in a methodological way, and their modeling and simulation, both at the circuit level and at the architectural level, are treated. In this way, the eleven contributions of this book combine in a unique way designs with methodologies and CAD that will be interesting to designers and CAD developers, both in industry and academia.

This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed. The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.

This book demonstrates why highly-digital CMOS time-encoding analog-to-digital converters incorporating voltage-controlled oscillators (VCOs) and time-to-digital converters (TDCs) are a good alternative to traditional switched-capacitor S-D modulators for power-efficient sensor, biomedical and communications applications. The authors describe the theoretical foundations and design methodology of such time-based ADCs from the basics to the latest developments. While most analog designers might notice some resemblance to PLL design, the book clearly highlights the differences to standard PLL circuit design and illustrates the design methodology with practical circuit design examples.Describes in detail the design methodology for CMOS time-encoding analog-to-digital converters that can be integrated along with digital logic in a nanometer System on Chip;Assists analog designers with the necessary change in design paradigm, highlighting differences between designing time-based ADCs and traditional analog circuits like switched-capacitor converters and PLLs;Uses a highly-visual, tutorial approach to the topic, including many practical examples of techniques introduced.

This book demonstrates why highly-digital CMOS time-encoding analog-to-digital converters incorporating voltage-controlled oscillators (VCOs) and time-to-digital converters (TDCs) are a good alternative to traditional switched-capacitor S-D modulators for power-efficient sensor, biomedical and communications applications. The authors describe the theoretical foundations and design methodology of such time-based ADCs from the basics to the latest developments. While most analog designers might notice some resemblance to PLL design, the book clearly highlights the differences to standard PLL circuit design and illustrates the design methodology with practical circuit design examples.Describes in detail the design methodology for CMOS time-encoding analog-to-digital converters that can be integrated along with digital logic in a nanometer System on Chip;Assists analog designers with the necessary change in design paradigm, highlighting differences between designing time-based ADCs and traditional analog circuits like switched-capacitor converters and PLLs;Uses a highly-visual, tutorial approach to the topic, including many practical examples of techniques introduced.

This book provides novel theoretical foundations and experimental demonstrations of Spiking Neural Networks (SNNs) in tasks such as radar gesture recognition for IoT devices and autonomous drone navigation using a fusion of retina-inspired event-based camera and radar sensing.

This book provides novel theoretical foundations and experimental demonstrations of Spiking Neural Networks (SNNs) in tasks such as radar gesture recognition for IoT devices and autonomous drone navigation using a fusion of retina-inspired event-based camera and radar sensing. The authors describe important new findings about the Spike-Timing-Dependent Plasticity (STDP) learning rule, which is widely believed to be one of the key learning mechanisms taking place in the brain. Readers will be enabled to create novel classes of edge AI and robotics applications, using highly energy- and area-efficient SNNs

This book describes the analysis and design of event-driven processing circuits in the mixed-signal domain, which aim to directly reduce the amount of system data when sampling the data.

Electronic skin (e-skin) is an emerging technology that can be applied in the fields of medical prosthetics and robotics: e-skin provides the sense of touch to mechanical systems. This book bridges the gap between existing e-skin technologies and the remarkable capabilities of human tactile perception. It presents end-to-end design strategies for next-generation fully-integrated e-skin systems that mirror essential properties of human skin, such as being multi-modal, multi-scale, and performing local processing. Building on a pragmatic, technology-aware neuromorphic design approach, that draws inspiration from biology without blindly replicating it, the book shows the system-level benefits of event-based approaches through temporal compression of tactile data via spikes, and it explains how spike-based representations support efficient neuromorphic processing with spiking neural networks, relaxing readout design constraints. Two validated e-skin chips, called INTUITIVE and DERMIS, are presented. They form a pathway toward e-skin systems with human-like tactile perception and embedded intelligence, combining high-resolution texture sensing with low-latency, large-area slip detection to bring electronic skin closer to the capabilities of the human skin.

This book investigates the possible circuit solutions to overcome the temperature and supply voltage-sensitivity of fully-integrated time references for ultra-low-power communication in wireless sensor networks. The authors provide an elaborate theoretical introduction and literature study to enable full understanding of the design challenges and shortcomings of current oscillator implementations. Furthermore, a closer look to the short-term as well as the long-term frequency stability of integrated oscillators is taken. Next, a design strategy is developed and applied to 5 different oscillator topologies and 1 sensor interface. All 6 implementations are subject to an elaborate study of frequency stability, phase noise and power consumption. In the final chapter all blocks are compared to the state of the art.

This book investigates the possible circuit solutions to overcome the temperature and supply voltage-sensitivity of fully-integrated time references for ultra-low-power communication in wireless sensor networks. The authors provide an elaborate theoretical introduction and literature study to enable full understanding of the design challenges and shortcomings of current oscillator implementations. Furthermore, a closer look to the short-term as well as the long-term frequency stability of integrated oscillators is taken. Next, a design strategy is developed and applied to 5 different oscillator topologies and 1 sensor interface. All 6 implementations are subject to an elaborate study of frequency stability, phase noise and power consumption. In the final chapter all blocks are compared to the state of the art.

This book discusses both architecture- and circuit-level design aspects of voltage-controlled-oscillator (VCO)-based analog-to-digital converters (ADCs), especially focusing on mitigation of VCO nonlinearity and the improvement of power efficiency. It shows readers how to develop power-efficient complementary-metal-oxide-semiconductor (CMOS) ADCs for applications such as LTE, 802.11n, and VDSL2+. The material covered can also be applied to other specifications and technologies.Design of Power-Efficient Highly Digital Analog-to-Digital Converters for Next-Generation Wireless Communication Systems begins with a general introduction to the applications of an ADC in communications systems and the basic concepts of VCO-based ADCs. The text addresses a wide range of converter architectures including open- and closed-loop technologies. Special attention is paid to the replacement of power-hungry analog blocks with VCO-based circuits and to the mitigation of VCO nonlinearity. Various MATLAB®/Simulink® models are provided for important circuit nonidealities, allowing designers and researchers to determine the required specifications for the different building blocks that form the systematic integrated-circuit design procedure.Five different VCO-based ADC design examples are presented, introducing innovations at both architecture and circuit levels. Of these designs, the best power efficiency of a high-bandwidth oversampling ADC is achieved in a 40 nm CMOS demonstration.This book is essential reading material for engineers and researchers working on low-power-analog and mixed-signal design and may be used by instructors teaching advanced courses on the subject. It provides a clear overview and comparison of VCO-based ADC architectures and gives the reader insight into the most important circuit imperfections.