Michiel Steyaert - Böcker

This tenth volume of Analog Circuit Design concentrates on 3 topics: 1. Scalable Analog Circuits, 2. High-Speed D/A Converters, and 3. RF Power Amplifiers. Each topic is covered by 6 papers, written by internationally recognized experts on that topic. These papers have a tutorial nature aimed at improving the design of analog circuits. The book is divided into three parts: Part I, Scalable Analog Circuit Design describes in 6 papers issues of: scalable high-speed design, scalable high-resolution mixed-mode ADC and OpAmp design, scalable high-voltage design for XDSL, scalability of wire-line front ends, reusable IP analog design, and porting CAD analog design. Part II, High-Speed D/A Converters describes in 6 papers issues of: Introduction to high-speed D/A converter design, retargetable 12-bit 200-MHz CMOS current steering design, high-speed CMOS D/A converters for upstream cable applications, static and dynamic performance limitations, the linearity challenge of D/A converters for communications, and a 400-MHz, 10-bit charge-domain CMOS D/A converter for low-spurious frequency synthesis.Part III, RF Power Amplifiers describes in 6 papers issues of: system aspects, overview and trade-offs, linear transmitter architectures, GaAs microwave SSPAs, Monolithic transformer-coupling in Si-bipolar, and RF power amplifier design in CMOS.

This volume deals with the design of the receive path of a highly-integrated CMOS cellular transceiver for the GSM-1800 cellular system. The complete design trajectory is covered, starting from the documents describing the standard down to the systematic development of CMOS receiver ICs that comply to the standard. The design of CMOS receivers is tackled at all abstraction levels: from architecture level, via circuit level, down to the device level and the other way around.

The boom in the mobile telecommunication market has captured the interest of electronic and communication companies worldwide. In order to cut costs, and to decrease volume and power consumption, research is ongoing which focuses on the integration of a complete RF transceiver on a single die. This book discusses an important building block in such a single-chip wireless transceiver, that is, the frequency synthesizer. The text starts off with a comprehensive overview of possible synthesizer architectures together with a discussion of the general PLL theory. It goes on to present an easy calculation method of predicting LC-tuned VCO phase noise. Practical designs are presented which illustrate in detail the implementation of monolithic LC-tuned VCOs, using either bonding-wire inductors or hollow planar inductors. It is demonstrated that such designs can achieve the required phase noise specifications using standard CMOS technology. The book also discusses the other PLL building blocks such as the high-speed frequency divider.The phase-switching multi-modulus prescaler architecture, which combines high input frequencies with a programmable division factor, is presented in chapter Six. A concluding chapter combines all the gathered knowledge and presents the first monolithic standard CMOS frequency synthesizer that achieves the DCS-1800 specifications.

This text investigates the feasibility of designing delta-sigma analogue to digital converters for very low supply voltage and low power operation in standard CMOS processes. The chosen technique of implementation is the Switched Opamp Technique which provides switched capacitor operation at low supply voltage without the need to apply voltage multipliers or low VtMOST devices. A method of implementing the classic single loop and cascaded delta-sigma modulator topologies with half delay integrators is presented. Those topologies are studied in order to find the parameters that maximize the performance in terms of peak SNR. Based on a linear model, the performance degradations of higher order single loop and cascaded modulators, compared to a hypothetical ideal modulator, are quantified. An overview of low voltage switched capacitor design techniques, such as the use of voltage multipliers, low VtMOST devices and the Switched Opamp Technique, is given.A discussion of the present status of the Switched Opamp Technique covers the single-ended Original Switched Opamp Technique, the Modified Switched Opamp Technique, which allows lower supply voltage operation, and differential implementation including common mode control techniques. The restrictions imposed on the analogue circuits by low supply voltage operation are investigated. Several low voltage circuit building blocks, some of which are new, are discussed. A new low voltage class AB OTA, especially suited for differential Switched Opamp applications, together with a common mode feedback amplifier and a comparator are presented and analyzed. As part of a systematic top-down design approach, the non-ideal charge transfer of the Switched Opamp integrator cell is modelled, based upon several models of the main opamp non-ideal characteristics. Behavioural simulations carried out with these models yield the required opamp specifications that ensure that the intended performance is met in an implementation. A power consumption analysis is performed. The influence of all design parameters, especially the low power supply voltage, is highlighted.Design guidelines towards low power operation are distilled. Two implementations are presented together with measurement results. The first one is a single-ended implementation of a delta-sigma ADC operating with 1.5V supply voltage and consuming 100 mW for a 74 dB dynamic range in a 3.4 kHz bandwidth. The second implementation is differential and operates with 900 mV. It achieves 77 dB dynamic range in 16 kHz bandwidth and consumes 40 mW. This book is a reference for analogue design engineers and researchers.

Devoted to the design of CMOS continuous-time filters, this book shows that CMOS is employed because the most complex integrated circuits have been realized with this technology for two decades. The most important advantages and drawbacks of continuous-time filters are clearly shown. The transfer function is one of the most important filter parameters but several others (like intermodulation distortion; power-supply rejection ratio; noise level and dynamic range) are fundamental in the design of high-performance systems. Special attention is paid to the practical aspects of the design, which shows the difference between an academic design and an industrial design. Step-by-step design procedures are often used to clarify the use of the techniques and topologies. The organisation of this text is hierarchical, starting with the design consideration of the basic building blocks and ending with the design of several high-performance continuous-time filters. Most of the circuits have been fabricated, theoretically analyzed and simulated, and silicon measurement results are compared with each other.This book can be used as a text book for senior or graduate courses in this field and can also be useful for industrial engineers.

When comparing conventional computing architectures to the architectures of biological neural systems, there are several striking differences. Conventional computers use a low number of high performance computing elements that are programmed with algorithms to perform tasks in a time sequenced way; they are very successful in administrative applications, in scientific simulations, and in certain signal processing applications. However, the biological systems still significantly outperform conventional computers in perception tasks, sensory data processing and motory control. Biological systems use a completely different computing paradigm: a massive network of simple processors that are (adaptively) interconnected and operate in parallel. This massively parallel processing seems the key aspect to their success. The advent of VLSI technologies has provided us with the technological means to implement very complicated systems on a silicon die. Analog VLSI circuits in standard digital technologies open the way for the implementation of massively parallel analog signal processing systems for sensory signal processing applications and for perception tasks.This text describes in depth the theory and practice of designing these massively parallel analog signal processing systems. Techniques are described which overcome the device and transistor mismatches which limit performance of the system. The book also shows how such a system can be efficiently implemented using cellular Neural Networks. 4

The revolution in wireless communications sets new requirements for transceivers (transmitter-receivers). Higher operating frequencies, lower power consumption and very high degree of integration, are specifications which require design approaches quite different from classical RF design techniques. The integratability and power consumption reduction of the digital component should further improve with the continued downscaling of technologies. This is, however, completely different for the analog transceiver front-end, the component which interfaces between the antenna and the digital signal processor. The analog front-end's integratability and power consumption are closely related to the physical limitations of the transceiver topology and not so much to the scaling of the used technology. Providing a comprehensive treatment of the design of transceivers for use in wireless communication systems, the book overviews existing transceiver design and goes on to introduce new multi-path receiver and transmitter topologies.It also presents a formal methodology for the high-level design of transceiver architectures and fully illustrates its use in the design of a low-IF/direct upconversion GSM transceiver front-end. This text further demonstrates its practical nature by containing concluding chapters which study both the integration of RF building blocks in CMOS and the capabilities of deep submicron CMOS used in combination with the new transceiver topologies for the implementation of wireless transceiver front-ends in the 1 to 2 GHz range.

Analog Circuit Design contains the contribution of 18 experts from the 13th International Workshop on Advances in Analog Circuit Design. It is number 13 in the successful series of Analog Circuit Design.It provides 18 excellent overviews of analog circuit design in: Sensor and Actuator Interfaces, Integrated High-Voltage Electronics and Power Management, and Low-Power and High-Resolution ADC’s.Analog Circuit Design is an essential reference source for analog circuits designers and researchers wishing to keep abreast with the latest developments in the field. The tutorial coverage also makes it suitable for use in an advanced design course.

LNA-ESD Co-Design for Fully Integrated CMOS Wireless Receivers fits in the quest for complete CMOS integration of wireless receiver front-ends. With a combined discussion of both RF and ESD performance, it tackles one of the final obstacles on the road to CMOS integration. The book is conceived as a design guide for those actively involved in the design of CMOS wireless receivers.The book starts with a comprehensive introduction to the performance requirements of low-noise amplifiers in wireless receivers. Several popular topologies are explained and compared with respect to future technology and frequency scaling. The ESD requirements are introduced and related to the state-of-the-art protection devices and circuits.LNA-ESD Co-Design for Fully Integrated CMOS Wireless Receivers provides an extensive theoretical treatment of the performance of CMOS low-noise amplifiers in the presence of ESD-protection circuitry. The influence of the ESD-protection parasitics on noise figure, gain, linearity, and matching are investigated. Several RF-ESD co-design solutions are discussed allowing both high RF-performance and good ESD-immunity for frequencies up to and beyond 5 GHz. Special attention is also paid to the layout of both active and passive components. LNA-ESD Co-Design for Fully Integrated CMOS Wireless Receivers offers the reader intuitive insight in the LNA’s behavior, as well as the necessary mathematical background to optimize its performance. All material is experimentally verified with several CMOS implementations, among which a fully integrated GPS receiver front-end. The book is essential reading for RF design engineers and researchers in the field and is also suitable as a text book for an advanced course on the subject.

Analog Circuit Design contains the contribution of 18 tutorials of the 14th workshop on Advances in Analog Circuit Design. Each part discusses a specific todate topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 14 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of analog circuit design, CAD and RF systems.Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design course.

Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS addresses the low-power low-voltage Sigma-Delta ADC design in nanometer CMOS technologies at both the circuit-level and the system level.The low-power low-voltage Sigma-Delta modulator design at the circuit level is introduced. A design example is presented in this book. This design is the first published Sigma-Delta design in a 90-nm CMOS technology and reaches a very high figure-of-merit. At the system level, a novel systematic study on the full feedforward Sigma-Delta topology is presented in this book. As a design example, a fourth-order single-loop full feedforward Sigma-Delta modulator design in a 130-nm pure digital CMOS technology is presented. This design is the first design using the full feedforward Sigma-Delta topology and reaches the highest conversion speed among all the 1-V Sigma-Delta modulators to date.

RF Power Amplifiers for Mobile Communications fits in the quest for fully integrated CMOS transceivers. The book tackles both high efficiency and high linearity PA design in low-voltage CMOS, and has a strong emphasis on theory, design and implementation. The book is conceived as a design guide for those actively involved in the design of CMOS wireless transceivers.RF Power Amplifiers for Mobile Communications starts from the basic theory of power amplification from the viewpoint of CMOS integration. The design of switching RF power amplifiers in CMOS is explored and CMOS PA design at low supply voltage using parallel amplification is discussed. Combining both efficiency and linearity is one of the major issues in CMOS PA design for wireless and mobile communications and is subsequently tackled. Different linearization techniques and approaches are discussed and polar modulation is clarified in greater detail. Finally, two CMOS PAimplementations are thoroughly covered. RF Power Amplifiers for Mobile Communications offers the reader an intuitive insight in Power Amplification as well as the necessary mathematical background. The book is essential reading for RF design engineers and researchers in the field and is also suitable as a text book for an advanced course on the subject.

Analog Circuit Design contains in total 18 tutorials. They reflect the contributions of 6 experts in each of the three fields covered by the three chapters mentioned in the subtitle, as presented at the 15th workshop on Advances in Analog Circuit Design (AACD) held in Maastricht, April 2006. This book is number 15 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of analog circuit design and related CAD, mainly in the fields of basic analog modules, mixed-signal electronics, AD and DA converters, RF systems, and automotive electronics.Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest developments in the field. The tutorial coverage also makes it suitable for use in an advanced design course.

Broadband Opto-Electrical Receivers in Standard CMOS fits in the quest for integrated opto-electrical solutions, and focuses on the receiver front-end. To further reduce the cost, the cheapest technology is selected: standard CMOS, without any optical tricks or flavors. The emphasis is on the analysis, design and implementation of high-performance analog receiver circuits. Broadband Opto-Electrical Receivers in Standard CMOS starts from the basic fundamentals, necessary for the design of opto-electronic interface circuits. The book continues with an in-depth analysis of the photodiode, transimpedance amplifier (TIA) and limiting amplifier (LA). To thoroughly understand the light detection mechanisms in silicon, first a one-dimensional and second a two-dimensional model is developed. Analytical design equations are derived to guide the design of the amplifying circuits. For the TIA, the focus lies on the sensitivity-speed trade-off. For the LA, a high gain-bandwidth is pursued. Several practical design examples reveal the subtleties and challenges encountered during the design of high-performance analog circuits.Broadband Opto-Electrical Receivers in Standard CMOS covers the total design flow of monolithic CMOS optical receivers.All material is experimentally verified with several CMOS implementations, with ultimately a fully integrated Gbit/s optical receiver front-end including photodiode, TIA and LA. The book is essential reading for analog design engineers and researchers in the field and is also suitable as a text book for an advanced course on the subject.

“Design of high voltage xDSL line drivers in standard CMOS” fits in the quest for highly efficient fully integrated xDSL modems for central office applications. The book focusses on the line driver, the most demanding building block of the xDSL modem for lowering power. To reduce the cost, the cheapest technology is selected: standard CMOS, without any extra process options to increase the nominal supply voltage. The emphasis lies on the analysis, design and implementation of high voltage highly efficient line drivers in mainstream CMOS.“Design of high voltage xDSL line drivers in standard CMOS” covers the total design flow of monolithic CMOS high voltage circuits. The book is essential reading for analog design engineers and researchers in the field and is also suitable as a text book for an advanced course on the subject.

This text discusses both architecture and circuit design aspects of Delta-Sigma A/D converters, with a special focus on multi-bit implementations. The emphasis is on high-speed high-resolution converters in CMOS for ADSL applications, although the material can also be applied for other specification goals and technologies. The book starts with a general introduction of the concepts of Delta-Sigma converters. A wide variety of architectures are discussed, ranging from single-loop to cascaded and various multi-bit topologies. These topologies are optimized to obtain stable converters with a high accuracy. A clear overview is provided of the maximum achievable performance of each topology, which allows a designer to select the optimal architecture for a certain specification. Special attention is paid to multi-bit architectures and possible solutions for the linearity problem of the DA converter in the feedback loop of converters. Several circuit design aspects of multi-bit Delta-Sigma converters are discussed. Various models are provided for a wide range of linear and non-linear circuit imperfections, which can degrade the performance of the converter.These models allow the designer to determine the required specifications for the different building blocks and form the basis of a systematic design procedure. The presented material is combined in a concluding chapter, which illustrates the systematic design procedure for two high-performance converters. Design of Multi-Bit Delta-Sigma A/D Converters provides a clear comparison of architectures and yields insight into the influence of the most important circuit non-idealities. It should allow you to design robust and high-performance Delta-Sigma AD converters in a shorter time.

This work contains the contribution of 18 tutorials of the 11th Workshop on Advances in Analog Circuit Design, providing information and overviews of analogue circuit design, CAD, and RF systems. These books can be seen as a reference to those people involved in analogue and mixed signal design. The idea is to discuses in each book three specific to-date topics on new and valuable design ideas in the area of analog circuit design. Each topic is discussed by six experts in that field and state of the art information is shared and overviewed. In this 11th edition the topics are: structured-mixed-mode design, multi-bit sigma-delta converters and short range RF circuits.

This title was conceived as a manual for the design of fully integrated S fractional-N frequency synthesizers in CMOS with a focus on achieving a high spectral purity, that is, low-phase-noise and high spurious suppression. Fractional-N design is elaborated from specification derivation up to architectural and building block level and down to circuit level. CMOS Fractional-N Synthesizers starts with a comprehensive introduction to general frequency synthesis. Different architectures and synthesizer building blocks are discussed with their relative importance on synthesizer specifications. The process of synthesizer specification derivation is illustrated with the DCS-1800 standard as a general test case. The book tackles the design of fractional-N synthesizers in CMOS on circuit level as well as system level. The circuit level focuses on high-speed prescaler design up to 12 GHz in CMOS and on fully integrated, low-phase-noise LC-VCO design. High-Q inductor integration and simulation in CMOS is elaborated and flicker noise minimization techniques are presented, ranging from bias point choice to noise filtering techniques.On a higher level, a systematic design strategy has been developed that trades off all noise contributions and fast dynamics for integrated capacitance (area). Moreover, a theoretical S phase noise analysis is presented, extended with a fast non-linear analysis method to accurately predict the influence of PLL non-linearities on the spectral purity of the S fractional-N frequency synthesizers. CMOS Fractional-N Synthesizers covers the total design flow of monolithic CMOS fractional-N synthesizers with high spectral purity while providing insight in the most critical issues of monolithic fractional-N synthesis. All material is experimentally verified with several CMOS implementations, with ultimately a monolithic CMOS S-controlled fractional-N synthesizer, which was part of a CMOS DCS-1800 transceiver front-end.

The ever-decreasing feature size has continuously provided improved functionality at a reduced cost. As the feature size decreased, designs moved from digital microprocessors and application specific integrated circuits (ASICs) to systems-on-a-chip (SoC). The design capabilities of the designer however, have not been increased equally. Analog design tools are only just emerging, and the design of the small analog part in the hostile digital environment, has become a tremendous bottleneck. This text introduces a design methodology that can help to bridge the productivity gap. Two different types of designs, depending on the design challenge, have been identified: commodity IP and star IP. Each category requires a different approach to boost design productivity. Commodity IP blocks are well suited to be automated in an analog synthesis environment and provided as soft IP. The design knowledge is usually common knowledge, and reuse is high accounting for the setup time needed for the analog library.Star IP still changes as technology evolves and the design cost can only be reduced by following a systematic design approach supported by point tools to relieve the designer from error-prone, repetitive tasks, allowing him/her to focus on new ideas to push the limits of the design. To validate the presented methodologies, three different industrial-strength applications have been selected and designed accordingly. Firstly, a particle detector front-end for space applications has been designed and embedded in the AMGIE library for further re-use. Performance compares favourably to an earlier manual design. Starting from specification, a physical layout can be generated within a few days. Secondly, current-steering D/A converters have been selected as a test-engine for the design methodology of Star IP. A novel topology has been developed allowing full flexibility to the designer in terms of switching scheme. This allows the designer to implement the Q2 Random Walk switching scheme which averages out random and systematic errors resulting in the first intrinsic 14-bit linear D/A converter in CMOS technology. The overall design time was reduced from 11 to four weeks.A third and final test-case, an 8 bit 200MS/s interpolating/averaging A/D converter has been designed. Performance and design times compare favorably to an earlier manual design. All experiments prove that despite general disbelieve, design cost can be reduced considerably, without compromising performance, by adopting the proper design methodology.

This is a practical guide and introduction to the design of key RF building blocks used in high data rate transmitters. The emphasis lies on CMOS circuit techniques applicable to oscillators and upconvertors. Furthermore, a method for RF-specific design automation is exemplified by the CYCLONE tool for automated LC-VCO synthesis. The accuracy of a simulation depends strongly on the models used for the passive and active components. Therefore, a chapter on practical RF simulation models for MOST devices and planar inductors is included. Polyphase networks can be used for quadrature signal generation and as a complex filter. The book describes in detail the analytical calculations on such networks and includes a practical simulation-based design approach. The final manufacturing step before measuring a chip is the bonding process. In a short chapter the flip-chip bonding technique is discussed and the negative influence of X-ray inspection on chip performance is demonstrated. High data rate systems need low phase-noise oscillators.The design of a 17GHz VCO as presented in this book demonstrates the possible use of a CMOS technology for fixed-wireless or high-speed optical system integration. Using a polyphase network as a complex filter, a ringoscillator with over a decade of tuning range has been linearized for use in HFC-like cable systems. This technique is discussed elaborately in a chapter on broadband oscillators. As a typical design case of a high data rate building block, the design of a wideband CMOS transmitter circuit is presented. Starting from a market overview, the target specifications are derived. A high-level circuit design is then gradually refined down to transistor level and ultimately layout. In a concluding chapter, the measured performance is discussed.

Number 12 in the successful series of Analog Circuit Design provides valuable information and excellent overviews of analogue circuit design, CAD and RF systems. The series is an ideal reference for those involved in analogue and mixed-signal design.

Design and Analysis of High Efficiency Line Drivers for xDSL covers the most important building block of an xDSL (ADSL, VDSL, ) system: the line driver. Traditional Class AB line drivers consume more than 70 per cent of the total power budget of state-of-the-art ADSL modems. This book describes the main difficulties in designing line drivers for xDSL. The most important specifications are elaborated staring from the main properties of the channel and the signal properties. The traditional (class AB), state-of-the-art (class G) and future technologies (class K) are discussed. The main part of Design and Analysis of High Efficiency Line Drivers for xDSL describes the design of a novel architecture: the Self-Oscillating Power Amplifier or SOPA. This architecture uses a non-linear, asynchronous modulation scheme that enables highly efficient, highly linear transmission. The concept has been proven by two implementations in a digital CMOS technology: a G-Lite compliant line driver with 61 per cent efficiency and a full ADSL-VDSL downstream compliant power amplifier with 47 per cent power efficiency. The proposed architecture is fully analysed and complete design plans including CMOS sca

Static and Dynamic Performance Limitations for High Speed D/A Converters discusses the design and implementation of high speed current-steering CMOS digital-to-analog converters. Starting from the definition of the basic specifications for a D/A converter, the elements determining the static and dynamic performance are identified. Different guidelines based on scientific derivations are suggested to optimize this performance. Furthermore, a new closed formula has been derived to account for the influence of the transistor mismatch on the achievable resolution of the current-steering D/A converter. To allow a thorough understanding of the dynamic behavior, a new factor has been introduced. Moreover, the frequency dependency of the output impedance introduces harmonic distortion components which can limit the maximum attainable spurious free dynamic range. The validity of all the derived concepts has been demonstrated in the design and implementation of different D/A converters ranging from high resolution to high speed devices, which also resulted in the first published 10 bit 1GSample/s CMOS current-steering D/A converter.Finally, the last part of the book gives an overview on different existing transistor mismatch models and the link with the static performance of the D/A converter. Static and Dynamic Performance Limitations for High Speed D/A Converters serves as an invaluable reference book and may be used as a text for advanced courses on the subject.

Analog Circuit Design is based on the yearly Advances in Analog Circuit Design workshop. The aim of the workshop is to bring together designers of advanced analogue and RF circuits for the purpose of studying and discussing new possibilities and future developments in this field. Selected topics for AACD 2007 are: (1) Sensors, Actuators and Power Drivers for the Automotive and Industrial Environment (Tue 27 March) - Chaired by Herman Casier, AMI Semiconductor Fellow, Belgium; (2) Integrated PA's from Wireline to RF (Wed 28 March) - Chaired by Prof. Michiel Steyaert, Catholic University, Leuven; (3) Very High Frequency Front Ends (Thu 29 March) - Chaired by Prof. Arthur van Roermund, Eindhoven University of Technology.

Analog Circuit Design contains the contribution of 18 tutorials of the 17th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 17 in this successful series of Analog Circuit Design.

This tenth volume of Analog Circuit Design concentrates on 3 topics: 1. Scalable Analog Circuits, 2. High-Speed D/A Converters, and 3. RF Power Amplifiers. Each topic is covered by 6 papers, written by internationally recognized experts on that topic. These papers have a tutorial nature aimed at improving the design of analog circuits. The book is divided into three parts: Part I, Scalable Analog Circuit Design describes in 6 papers issues of: scalable high-speed design, scalable high-resolution mixed-mode ADC and OpAmp design, scalable high-voltage design for XDSL, scalability of wire-line front ends, reusable IP analog design, and porting CAD analog design. Part II, High-Speed D/A Converters describes in 6 papers issues of: Introduction to high-speed D/A converter design, retargetable 12-bit 200-MHz CMOS current steering design, high-speed CMOS D/A converters for upstream cable applications, static and dynamic performance limitations, the linearity challenge of D/A converters for communications, and a 400-MHz, 10-bit charge-domain CMOS D/A converter for low-spurious frequency synthesis.Part III, RF Power Amplifiers describes in 6 papers issues of: system aspects, overview and trade-offs, linear transmitter architectures, GaAs microwave SSPAs, Monolithic transformer-coupling in Si-bipolar, and RF power amplifier design in CMOS.

CMOS Cellular Receiver Front-Ends: from Specification to Realization deals with the design of the receive path of a highly-integrated CMOS cellular transceiver for the GSM-1800 cellular system.

The recent boom in the mobile telecommunication market has captured the interest of electronic and communication companies worldwide. In order to cut costs, and to decrease volume and power consumption, research is ongoing which focuses on the integration of a complete RF transceiver on a single die. This book discusses for the first time an important building block in such a single-chip wireless transceiver, that is, the frequency synthesizer. CMOS Wireless Frequency Synthesizer Design starts off with a comprehensive overview of possible synthesizer architectures together with a discussion of the general PLL theory. It goes on to present an easy calculation method of predicting LC-tuned VCO phase noise. Practical designs are presented which illustrate in detail the implementation of monolithic LC-tuned VCOs, using either bonding-wire inductors or hollow planar inductors. It is demonstrated that such designs can achieve the required phase noise specifications using standard CMOS technology. CMOS Wireless Frequency Synthesizer Design also discusses the other PLL building blocks such as the high-speed frequency divider.The phase-switching multi-modulus prescaler architecture, which combines high input frequencies with a programmable division factor, is presented in chapter 6. A concluding chapter combines all the gathered knowledge and presents the first monolithic standard CMOS frequency synthesizer that achieves the DCS-1800 specifications. CMOS Wireless Frequency Synthesizer Design is essential reading for all researchers and practicing engineers working in the design of wireless communication systems requiring highly integrated RF transceivers and frequency synthesizers.

Design of Low-Voltage Low-Power CMOS Delta-Sigma A/D Converters investigates the feasibility of designing Delta-Sigma Analog to Digital Converters for very low supply voltage (lower than 1.5V) and low power operation in standard CMOS processes. The chosen technique of implementation is the Switched Opamp Technique which provides Switched Capacitor operation at low supply voltage without the need to apply voltage multipliers or low VtMOST devices. A method of implementing the classic single loop and cascaded Delta-Sigma modulator topologies with half delay integrators is presented. Those topologies are studied in order to find the parameters that maximise the performance in terms of peak SNR. Based on a linear model, the performance degradations of higher order single loop and cascaded modulators, compared to a hypothetical ideal modulator, are quantified. An overview of low voltage Switched Capacitor design techniques, such as the use of voltage multipliers, low VtMOST devices and the Switched Opamp Technique, is given.An in-depth discussion of the present status of the Switched Opamp Technique covers the single-ended Original Switched Opamp Technique, the Modified Switched Opamp Technique, which allows lower supply voltage operation, and differential implementation including common mode control techniques. The restrictions imposed on the analog circuits by low supply voltage operation are investigated. Several low voltage circuit building blocks, some of which are new, are discussed. A new low voltage class AB OTA, especially suited for differential Switched Opamp applications, together with a common mode feedback amplifier and a comparator are presented and analyzed. As part of a systematic top-down design approach, the non-ideal charge transfer of the Switched Opamp integrator cell is modeled, based upon several models of the main opamp non-ideal characteristics. Behavioral simulations carried out with these models yield the required opamp specifications that ensure that the intended performance is met in an implementation. A power consumption analysis is performed. The influence of all design parameters, especially the low power supply voltage, is highlighted.Design guidelines towards low power operation are distilled. Two implementations are presented together with measurement results. The first one is a single-ended implementation of a Delta-Sigma ADC operating with 1.5V supply voltage and consuming 100 mW for a 74 dB dynamic range in a 3.4 kHz bandwidth. The second implementation is differential and operates with 900 mV. It achieves 77 dB dynamic range in 16 kHz bandwidth and consumes 40 mW. Design of Low-Voltage Low-Power CMOS Delta-Sigma A/D Converters is essential reading for analog design engineers and researchers.