Jean-Michel Sallese - Böcker

The first book on the topic, this is a comprehensive introduction to the modeling and design of junctionless field effect transistors (FETs). Beginning with a discussion of the advantages and limitations of the technology, the authors also provide a thorough overview of published analytical models for double-gate and nanowire configurations, before offering a general introduction to the EPFL charge-based model of junctionless FETs. Important features are introduced gradually, including nanowire versus double-gate equivalence, technological design space, junctionless FET performances, short channel effects, transcapacitances, asymmetric operation, thermal noise, interface traps, and the junction FET. Additional features compatible with biosensor applications are also discussed. This is a valuable resource for students and researchers looking to understand more about this new and fast developing field.

This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools.The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits.The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis.Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits;Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate;Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices;Offers design guidelines to reduce couplings by adding specific protections.