Maher Kayal - Böcker

Features contributions on developments and challenges in research and education on microelectronics, microsystems and related areas. This book is intended for professors, researchers and PhDs involved in microelectronics and/or in electrical engineering, microsystems and material sciences.

Methodology for the Digital Calibration of Analog Circuits and Systems shows how to relax the extreme design constraints in analog circuits, allowing the realization of high-precision systems even with low-performance components. A complete methodology is proposed, and three applications are detailed.To start with, an in-depth analysis of existing compensation techniques for analog circuit imperfections is carried out. The M/2+M sub-binary digital-to-analog converter is thoroughly studied, and the use of this very low-area circuit in conjunction with a successive approximations algorithm for digital compensation is described. A complete methodology based on this compensation circuit and algorithm is then proposed. The detection and correction of analog circuit imperfections is studied, and a simulation tool allowing the transparent simulation of analog circuits with automatic compensation blocks is introduced. The first application shows how the sub-binary M/2+M structure can be employed as a conventional digital-to-analog converter if two calibration and radix conversion algorithms are implemented.The second application, a SOI 1T DRAM, is then presented. A digital algorithm chooses a suitable reference value that compensates several circuit imperfections together, from the sense amplifier offset to the dispersion of the memory read currents.The third application is the calibration of the sensitivity of a current measurement microsystem based on a Hall magnetic field sensor. Using a variant of the chopper modulation, the spinning current technique, combined with a second modulation of a reference signal, the sensitivity of the complete system is continuously measured without interrupting normal operation. A thermal drift lower than 50 ppm/°C is achieved, which is 6 to 10 times less than in state-of-the-art implementations. Furthermore, the calibration technique alsocompensates drifts due to mechanical stresses and ageing.

Structured Analog CMOS Design describes a structured analog design approach that makes it possible to simplify complex analog design problems and develop a design strategy that can be used for the design of large number of analog cells. It intentionally avoids treating the analog design as a mathematical problem, developing a design procedure based on the understanding of device physics and approximations that give insight into parameter interdependences.The basic design concept consists in analog cell partitioning into the basic analog structures and sizing of these basic analog structures in a predefined procedural design sequence. The procedural design sequence ensures the correct propagation of design specifications, the verification of parameter limits and the local optimization loops. The proposed design procedure is also implemented as a CAD tool that follows this book.

This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools.The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits.The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis.Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits;Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate;Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices;Offers design guidelines to reduce couplings by adding specific protections.

This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools.The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits.The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis.Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits;Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate;Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices;Offers design guidelines to reduce couplings by adding specific protections.

Methodology for the Digital Calibration of Analog Circuits and Systems shows how to relax the extreme design constraints in analog circuits, allowing the realization of high-precision systems even with low-performance components. A complete methodology is proposed, and three applications are detailed.To start with, an in-depth analysis of existing compensation techniques for analog circuit imperfections is carried out. The M/2+M sub-binary digital-to-analog converter is thoroughly studied, and the use of this very low-area circuit in conjunction with a successive approximations algorithm for digital compensation is described. A complete methodology based on this compensation circuit and algorithm is then proposed. The detection and correction of analog circuit imperfections is studied, and a simulation tool allowing the transparent simulation of analog circuits with automatic compensation blocks is introduced. The first application shows how the sub-binary M/2+M structure can be employed as a conventional digital-to-analog converter if two calibration and radix conversion algorithms are implemented.The second application, a SOI 1T DRAM, is then presented. A digital algorithm chooses a suitable reference value that compensates several circuit imperfections together, from the sense amplifier offset to the dispersion of the memory read currents.The third application is the calibration of the sensitivity of a current measurement microsystem based on a Hall magnetic field sensor. Using a variant of the chopper modulation, the spinning current technique, combined with a second modulation of a reference signal, the sensitivity of the complete system is continuously measured without interrupting normal operation. A thermal drift lower than 50 ppm/°C is achieved, which is 6 to 10 times less than in state-of-the-art implementations. Furthermore, the calibration technique alsocompensates drifts due to mechanical stresses and ageing.

Structured Analog CMOS Design describes a structured analog design approach that makes it possible to simplify complex analog design problems and develop a design strategy that can be used for the design of large number of analog cells. It intentionally avoids treating the analog design as a mathematical problem, developing a design procedure based on the understanding of device physics and approximations that give insight into parameter interdependences.The basic design concept consists in analog cell partitioning into the basic analog structures and sizing of these basic analog structures in a predefined procedural design sequence. The procedural design sequence ensures the correct propagation of design specifications, the verification of parameter limits and the local optimization loops. The proposed design procedure is also implemented as a CAD tool that follows this book.

Advances in electronics have pushed mankind to create devices, ranging from - credible gadgets to medical equipment to spacecraft instruments. More than that, modern society is getting used to—if not dependent on—the comfort, solutions, and astonishing amount of information brought by these devices. One ?eld that has continuously bene?tted from those advances is the radio frequency integrated c- cuit (RFIC) design, which in its turn has promoted countless bene?ts to the mankind as a payback. Wireless communications is one prominent example of what the - vances in electronics have enabled and their consequences to our daily life. How could anyone back in the eighties think of the possibilities opened by the wireless local area networks (WLANs) that can be found today in a host of places, such as public libraries, coffee shops, trains, to name just a few? How can a youngster, who lives this true WLAN experience nowadays, imagine a world without it? This book dealswith the design oflinearCMOS RF PowerAmpli?ers(PAs). The RF PA is a very important part of the RF transceiver, the device that enables wireless communications. Two important aspects that are key to keep the advances in RF PA design at an accelerate pace are treated: ef?ciency enhancement and frequen- tunable capability. For this purpose, the design of two different integrated circuits realizedina0. 11µmtechnologyispresented,eachoneaddressingadifferentaspect. With respect to ef?ciency enhancement, the design of a dynamic supply RF power ampli?er is treated, making up the material of Chaps. 2 to 4.

Advances in electronics have pushed mankind to create devices, ranging from - credible gadgets to medical equipment to spacecraft instruments. More than that, modern society is getting used to—if not dependent on—the comfort, solutions, and astonishing amount of information brought by these devices. One ?eld that has continuously bene?tted from those advances is the radio frequency integrated c- cuit (RFIC) design, which in its turn has promoted countless bene?ts to the mankind as a payback. Wireless communications is one prominent example of what the - vances in electronics have enabled and their consequences to our daily life. How could anyone back in the eighties think of the possibilities opened by the wireless local area networks (WLANs) that can be found today in a host of places, such as public libraries, coffee shops, trains, to name just a few? How can a youngster, who lives this true WLAN experience nowadays, imagine a world without it? This book dealswith the design oflinearCMOS RF PowerAmpli?ers(PAs). The RF PA is a very important part of the RF transceiver, the device that enables wireless communications. Two important aspects that are key to keep the advances in RF PA design at an accelerate pace are treated: ef?ciency enhancement and frequen- tunable capability. For this purpose, the design of two different integrated circuits realizedina0. 11µmtechnologyispresented,eachoneaddressingadifferentaspect. With respect to ef?ciency enhancement, the design of a dynamic supply RF power ampli?er is treated, making up the material of Chaps. 2 to 4.