Larysa Titarenko – författare

This book is devoted to the logic synthesis of field programmable gate array (FPGA)-based circuits of Mealy finite state machines (FSM). Three new methods of state assignment are proposed, which allows obtaining FSM circuits required minimum amount of internal chip resources.

Logic Synthesis for FPGA-Based Mealy Finite State Machines: Structural Decomposition in Logic Design contains several original synthesis and optimization methods based on the structural decomposition of FPGA-based FSM circuits developed by the authors. To optimize FSM circuits, the authors introduce the use of three methods of state assignment: twofold, extended, and composite. These methods allow for the creation of two- or three-level architectures of FSM circuits. The authors also demonstrate how the proposed methods, FSM architectures and synthesis methods can replace known solutions based on either functional decomposition or classical methods of structural decomposition. The authors also show how these architectures have regular systems of interconnections and demonstrate positive features compared to methods based on functional decomposition, including producing circuits with fewer elements that are faster and consume less power than their counterparts. The book includes experimental results proving the efficiency of the proposed solutions and compares the numbers in Look-up Tables (LUTs), showing the performance (maximum operating frequency) and power consumption for various methods of state assignment.

The audience for this book is students, researchers, and engineers specializing in computer science/ engineering, electronics, and telecommunications. It will be especially useful for engineers working within the scope of algorithms, hardware-based software accelerators and control units, and systems based on the use of FPGAs.

This book is devoted to the logic synthesis of field programmable gate array (FPGA)-based circuits of Mealy finite state machines (FSM). Three new methods of state assignment are proposed, which allows obtaining FSM circuits required minimum amount of internal chip resources.

Logic Synthesis for FPGA-Based Mealy Finite State Machines: Structural Decomposition in Logic Design contains several original synthesis and optimization methods based on the structural decomposition of FPGA-based FSM circuits developed by the authors. To optimize FSM circuits, the authors introduce the use of three methods of state assignment: twofold, extended, and composite. These methods allow for the creation of two- or three-level architectures of FSM circuits. The authors also demonstrate how the proposed methods, FSM architectures and synthesis methods can replace known solutions based on either functional decomposition or classical methods of structural decomposition. The authors also show how these architectures have regular systems of interconnections and demonstrate positive features compared to methods based on functional decomposition, including producing circuits with fewer elements that are faster and consume less power than their counterparts. The book includes experimental results proving the efficiency of the proposed solutions and compares the numbers in Look-up Tables (LUTs), showing the performance (maximum operating frequency) and power consumption for various methods of state assignment.

The audience for this book is students, researchers, and engineers specializing in computer science/ engineering, electronics, and telecommunications. It will be especially useful for engineers working within the scope of algorithms, hardware-based software accelerators and control units, and systems based on the use of FPGAs.

This book focuses on control units, which are a vital part of modern digital systems, and responsible for the efficiency of controlled systems. The model of a finite state machine (FSM) is often used to represent the behavior of a control unit. As a rule, control units have irregular structures that make it impossible to design their logic circuits using the standard library cells. Design methods depend strongly on such factors as the FSM used, specific features of the logic elements implemented in the FSM logic circuit, and the characteristics of the control algorithm to be interpreted.

This book discusses Moore and Mealy FSMs implemented with FPGA chips, including look-up table elements (LUT) and embedded memory blocks (EMB). It is crucial to minimize the number of LUTs and EMBs in an FSM logic circuit, as well as to make the interconnections between the logic elements more regular, and various methods of structural decompositions can be used to solve this problem. These methods are reduced to the presentation of an FSM circuit as a composition of different logic blocks, the majority of which implement systems of intermediate logic functions different (and much simpler) than input memory functions and FSM output functions. The structural decomposition results in multilevel FSM circuits having fewer logic elements than equivalent single-level circuits. The book describes well-known methods of structural decomposition and proposes new ones, examining their impact on the final amount of hardware in an FSM circuit. It is of interest to students and postgraduates in the area of Computer Science, as well as experts involved in designing digital systems with complex control units. The proposed models and design methods open new possibilities for creating logic circuits of control units with an optimal amount of hardware and regular interconnections.

The book is composed of two parts. The first part introduces the concepts of the design of digital systems using contemporary field-programmable gate arrays (FPGAs). Various design techniques are discussed and illustrated by examples. The operation and effectiveness of these techniques is demonstrated through experiments that use relatively cheap prototyping boards that are widely available. The book begins with easily understandable introductory sections, continues with commonly used digital circuits, and then gradually extends to more advanced topics. The advanced topics include novel techniques where parallelism is applied extensively. These techniques involve not only core reconfigurable logical elements, but also use embedded blocks such as memories and digital signal processing slices and interactions with general-purpose and application-specific computing systems. Fully synthesizable specifications are provided in a hardware-description language (VHDL) and are ready to be tested and incorporated in engineering designs. A number of practical applications are discussed from areas such as data processing and vector-based computations (e.g. Hamming weight counters/comparators). The second part of the book covers the more theoretical aspects of finite state machine synthesis with the main objective of reducing basic FPGA resources, minimizing delays and achieving greater optimization of circuits and systems.

This book discusses control units represented by the model of a finite state machine (FSM). It contains various original methods and takes into account the peculiarities of field-programmable gate arrays (FPGA) chips and a FSM model. It shows that one of the peculiarities of FPGA chips is the existence of embedded memory blocks (EMB). The book is devoted to the solution of problems of logic synthesis and reduction of hardware amount in control units. The book will be interesting and useful for researchers and PhD students in the area of Electrical Engineering and Computer Science, as well as for designers of modern digital systems.

This book discusses Moore finite state machines (FSMs) implemented with field programmable gate arrays (FPGAs) including look-up table (LUT) elements and embedded memory blocks (EMBs). To minimize the number of LUTs in FSM logic circuits, the authors propose replacing a state register with a state counter. They also put forward an approach allowing linear chains of states to be created, which simplifies the system of input memory functions and, therefore, decreases the number of LUTs in the resulting FSM circuit. The authors combine this approach with using EMBs to implement the system of output functions (microoperations). This allows a significant decrease in the number of LUTs, as well as eliminating a lot of interconnections in the FSM logic circuit. As a rule, it also reduces the area occupied by the circuit and diminishes the resulting power dissipation.

This book is an interesting and valuable resource for students and postgraduates in the area of computer science, as well as for designers of digital systems that included complex control units