Physical Design for 3D Integrated Circuits

Aida Todri-Sanial holds a BS in electrical engineering from Bradley University, IL; an MS in electrical engineering from California State University, Long Beach, CA; and a PhD in electrical and computer engineering from the University of California, Santa Barbara. She has held visiting research positions at Cadence Design Systems, Mentor Graphics, IBM TJ Watson Research Center, and STMicroelectronics. She was a recipient of the John Bardeen Fellowship and an R&D engineer at Fermilab, IL. She is currently a research scientist at CNRS, France and a member of the Microelectronics Department at LIRMM, where she is the group leader of Integration and Design of Energy-Aware Circuits and Systems. Widely published, highly decorated, and an IEEE and ACM member, Dr. Todri-Sanial participates in several international conference committees and serves as an associate editor for IEEE TVLSI journal. She is also engaged with the EPWS and WiTEC.Chuan Seng Tan holds a BEng in electrical engineering from the University of Malaya, Malaysia; an MEng in advanced materials from the National University of Singapore; and a PhD in electrical engineering from the Massachusetts Institute of Technology, Cambridge. He has been a research engineer with the Institute of Microelectronics, Singapore; an Applied Materials Graduate Fellow; and an intern at Intel Corporation, Oregon. He is currently an associate professor at Nanyang Technological University, Singapore, where he previously served as a Lee Kuan Yew Postdoctoral Fellow and an inaugural Nanyang Assistant Professor. Widely published, Dr. Tan participates in several international conference committees and is a member of the IEEE. He has edited three and co-authored two books, and serves as an associate editor for Elsevier Microelectronics Journal.

• 2.5D/3D ICs: Drivers, Technology, Applications, and Outlook. Overview of Physical Design Issues for 3D-Integrated Circuits. Detailed Electrical and Reliability Study of Tapered TSVs. 3D Interconnect Extraction. 3D Placement and Routing. Power and Signal Integrity Challenges in 3D Systems-on-Chip. Design Methodology for TSV-Based 3D Clock Networks. Design Methodology for 3D Power Delivery Networks. Live Free or Die Hard: Design for Reliability in 3D Integrated Circuits. Thermal Modeling and Management for 3D Stacked Systems. Exploration of the Thermal Design Space in 3D Integrated Circuits. Dynamic Thermal Optimization for 3D Many-Core Systems. TSV-to-Device Noise Analysis and Mitigation Techniques. Overview of 3D CAD Design Tools. Design Challenges and Solutions for Monolithic 3D ICs. Design of High-Speed Interconnects for 3D/2.5D ICs without TSVs. Challenges and Future Directions of 3D Physical Design.