Robert W. Brodersen – författare

This collection of important papers provides a comprehensive overview of low-power system design, from component technologies and circuits to architecture, system design, and CAD techniques. LOW POWER CMOS DESIGN summarizes the key low-power contributions through papers written by experts in this evolving field.

This text begins with a description of the metrics and benchmarks used to design energy-efficient microprocessor systems, which is followed by energy efficient methodologies for the architecture and circuit design, DC-DC conversion, energy efficient software and system integration. Detailed design of the critical circuits and their performance is included throughout. "Energy Efficient Microprocessor Design" should be of interest to circuit designers as well as researchers in computer architecture and signal processing.

This is a study of the issues behind the development of a high-bandwidth, silicon-complementary, metal-oxide silicon (CMOS), low-power transceiver system for mobile RF wireless data communications. In the design of any RF communications system, three distinct factors must be considered: the propagation environment in question, the multiplexing and modulation of user data streams, and the complexity of hardware required to implement the desired link. None of these can be allowed to dominate. Coupling between system design and implementation, the key to the simultaneous achievement of high band-width and low power, is emphasized throughout the book. The material presented is the result of broad-band wireless-systems research carried out at the University of California, Berkeley. The wireless development was motivated by a much larger collaborative effort known as the Infopad Project, which was centred on the development of a mobile information terminal for multimedia content - a wireless "network computer".The desire for mobility, combined with the need to support potentially hundreds of users simultaneously accessing full-motion digital video, demanded a wireless solution that was of far lower power and higher data-rate than could be provided by existing systems. That solution is the topic of this book - a case study of not only wireless-systems designs, but also the implementation of such a link, down to the analogue and digital circuit level.

A silicon compiler is a software system which can automatically generate an integrated circuit from a user's specification. Anatomy of a Silicon Compiler examines one such compiler in detail, covering the basic framework and design entry, the actual algorithms and libraries which are used, the approach to verification and testing, behavioral synthesis tools and several applications which demonstrate the system's capabilities.

Power consumption has become a major design consideration for battery-operated, portable systems as well as high-performance, desktop systems. Strict limitations on power dissipation must be met by the designer while still meeting ever higher computational requirements. A comprehensive approach is thus required at all levels of system design, ranging from algorithms and architectures to the logic styles and the underlying technology. Potentially one of the most important techniques involves combining architecture optimization with voltage scaling, allowing a trade-off between silicon area and low-power operation. Architectural optimization enables supply voltages of the order of 1 V using standard CMOS technology. Several techniques can also be used to minimize the switched capacitance, including representation, optimizing signal correlations, minimizing spurious transitions, optimizing sequencing of operations, activity-driven power down, etc. The high- efficiency of DC-DC converter circuitry required for efficient, low-voltage and low-current level operation is described by Stratakos, Sullivan and Sanders. The application of various low-power techniques to a chip set for multimedia applications shows that orders-of-magnitude reduction in power consumption is possible. The book also features an analysis by Professor Meindl of the fundamental limits of power consumption achievable at all levels of the design hierarchy. Svensson, of ISI, describes emerging adiabatic switching techniques that can break the CV2f barrier and reduce the energy per computation at a fixed voltage. Srivastava, of AT&T, presents the application of aggressive shut-down techniques to microprocessor applications.

Research since the mid-1980s has brought about the development of high-performance systems such as powerful workstations, sophisticated computer graphics, and multimedia systems such as real-time video and speech recognition. A significant change in the attitude of users is the desire to have access to this computation at any location without the need to be connected to the wired power source. This has resulted in the growth of research and development in the area of wireless computing since the early-1990s. This text deals with several key technologies required for wireless computing. The topics covered include reliable wireless protocols, portable terminal design considerations, video coding, RF circuit design issues and tools, display technology, energy-efficient applications, specific and programmable design techniques, energy efficiency metrics, low-voltage process technology and circuit design considerations, and CAD tools for low-power design at the behavior, logic and physical design level. The book is an edited volume of original research comprising invited contributions by leading researchers.This research work has also been published as a special issue of the "Journal of VLSI Signal Processing Systems" (Volume 13, Numbers 2 & 3).

In DSP Architecture Design Essentials, authors Dejan Marković and Robert W. Brodersen cover a key subject for the successful realization of DSP algorithms for communications, multimedia, and healthcare applications. The book addresses the need for DSP architecture design that maps advanced DSP algorithms to hardware in the most power- and area-efficient way.The key feature of this text is a design methodology based on a high-level design model that leads to hardware implementation with minimum power and area. The methodology includes algorithm-level considerations such as automated word-length reduction and intrinsic data properties that can be leveraged to reduce hardware complexity. From a high-level data-flow graph model, an architecture exploration methodology based on linear programming is used to create an array of architectural solutions tailored to the underlying hardware technology.The book is supplemented with online material: bibliography, design examples, CAD tutorials and custom software.

Research over the last decade has brought about the development of high-performance systems such as powerful workstations, sophisticated computer graphics, and multimedia systems such as real-time video and speech recognition. A significant change in the attitude of users is the desire to have access to this computation at any location without the need to be connected to the wired power source. This has resulted in the explosive growth of research and development in the area of wireless computing over the last five years. Technologies for Wireless Computing deals with several key technologies required for wireless computing. The topics covered include reliable wireless protocols, portable terminal design considerations, video coding, RF circuit design issues and tools, display technology, energy-efficient applications, specific and programmable design techniques, energy efficiency metrics, low-voltage process technology and circuit design considerations, and CAD tools for low-power design at the behavior, logic and physical design level. Technologies for Wireless Computing is an edited volume of original research comprising invited contributions by leading researchers. This research work has also been published as a special issue of the Journal of VLSI Signal Processing Systems (Volume 13, Numbers 2 & 3).

Research over the last decade has brought about the development of high-performance systems such as powerful workstations, sophisticated computer graphics, and multimedia systems such as real-time video and speech recognition. A significant change in the attitude of users is the desire to have access to this computation at any location without the need to be connected to the wired power source. This has resulted in the explosive growth of research and development in the area of wireless computing over the last five years. Technologies for Wireless Computing deals with several key technologies required for wireless computing. The topics covered include reliable wireless protocols, portable terminal design considerations, video coding, RF circuit design issues and tools, display technology, energy-efficient applications, specific and programmable design techniques, energy efficiency metrics, low-voltage process technology and circuit design considerations, and CAD tools for low-power design at the behavior, logic and physical design level. Technologies for Wireless Computing is an edited volume of original research comprising invited contributions by leading researchers. This research work has also been published as a special issue of the Journal of VLSI Signal Processing Systems (Volume 13, Numbers 2 & 3).

This work began in 1995 as an outgrowth of the InfoPad project which showed us that in order to reduce the energy consumption of a portable multimedia terminal that something had to be done about the consumption of the microprocessor subsystem. The design of the InfoPad attempted to reduce the requirements of this general pur­ pose processor by moving the computation into the network or by the use of highly optimized integrated circuits, but in spite of these efforts it still was a major consumer of energy. The reasons for this became apparent as we determined that the energy required to perform a function in dedicated hardware could be several orders of magnitude lower than that consumed in the InfoPad microprocessor. We therefore set out on a full fledged attack on all aspects of the microprocessor energy consumption [1 J. After considerable analysis it became clear that though better circuit design and a stream­ lined architecture would assist in our goal of energy reduction, that the biggest gains were to be found by operating at reduced voltages. For the busses and VO this could be accomplished without significant degradation of the processor performance, but this was not a straightforward solution when applied to the core of the processor sub­ system (CPU and memory).

Power consumption has become a major design consideration for battery-operated, portable systems as well as high-performance, desktop systems. Strict limitations on power dissipation must be met by the designer while still meeting ever higher computational requirements. A comprehensive approach is thus required at all levels of system design, ranging from algorithms and architectures to the logic styles and the underlying technology. Potentially one of the most important techniques involves combining architecture optimization with voltage scaling, allowing a trade-off between silicon area and low-power operation. Architectural optimization enables supply voltages of the order of 1 V using standard CMOS technology. Several techniques can also be used to minimize the switched capacitance, including representation, optimizing signal correlations, minimizing spurious transitions, optimizing sequencing of operations, activity-driven power down, etc. The high- efficiency of DC-DC converter circuitry required for efficient, low-voltage and low-current level operation is described by Stratakos, Sullivan and Sanders. The application of various low-power techniques to a chip set for multimedia applications shows that orders-of-magnitude reduction in power consumption is possible. The book also features an analysis by Professor Meindl of the fundamental limits of power consumption achievable at all levels of the design hierarchy. Svensson, of ISI, describes emerging adiabatic switching techniques that can break the CV2f barrier and reduce the energy per computation at a fixed voltage. Srivastava, of AT&T, presents the application of aggressive shut-down techniques to microprocessor applications.

A silicon compiler is a software system which can automatically generate an integrated circuit from a user's specification. Anatomy of a Silicon Compiler examines one such compiler in detail, covering the basic framework and design entry, the actual algorithms and libraries which are used, the approach to verification and testing, behavioral synthesis tools and several applications which demonstrate the system's capabilities.

Low-Power CMOS Wireless Communications: A Wideband CDMA System Design focuses on the issues behind the development of a high-bandwidth, silicon complementary metal-oxide silicon (CMOS) low-power transceiver system for mobile RF wireless data communications. In the design of any RF communications system, three distinct factors must be considered: the propagation environment in question, the multiplexing and modulation of user data streams, and the complexity of hardware required to implement the desired link. None of these can be allowed to dominate. Coupling between system design and implementation is the key to simultaneously achieving high bandwidth and low power and is emphasized throughout the book. The material presented in Low-Power CMOS Wireless Communications: A Wideband CDMA System Design is the result of broadband wireless systems research done at the University of California, Berkeley. The wireless development was motivated by a much larger collaborative effort known as the Infopad Project, which was centered on developing a mobile information terminal for multimedia content - a wireless `network computer'. The desire for mobility, combined with the need to support potentially hundreds of users simultaneously accessing full-motion digital video, demanded a wireless solution that was of far lower power and higher data rate than could be provided by existing systems. That solution is the topic of this book: a case study of not only wireless systems designs, but also the implementation of such a link, down to the analog and digital circuit level.

This work began in 1995 as an outgrowth of the InfoPad project which showed us that in order to reduce the energy consumption of a portable multimedia terminal that something had to be done about the consumption of the microprocessor subsystem. The design of the InfoPad attempted to reduce the requirements of this general pur­ pose processor by moving the computation into the network or by the use of highly optimized integrated circuits, but in spite of these efforts it still was a major consumer of energy. The reasons for this became apparent as we determined that the energy required to perform a function in dedicated hardware could be several orders of magnitude lower than that consumed in the InfoPad microprocessor. We therefore set out on a full fledged attack on all aspects of the microprocessor energy consumption [1 J. After considerable analysis it became clear that though better circuit design and a stream­ lined architecture would assist in our goal of energy reduction, that the biggest gains were to be found by operating at reduced voltages. For the busses and VO this could be accomplished without significant degradation of the processor performance, but this was not a straightforward solution when applied to the core of the processor sub­ system (CPU and memory).

Power consumption has become a major design consideration for battery-operated, portable systems as well as high-performance, desktop systems. Strict limitations on power dissipation must be met by the designer while still meeting ever higher computational requirements. A comprehensive approach is thus required at all levels of system design, ranging from algorithms and architectures to the logic styles and the underlying technology. Potentially one of the most important techniques involves combining architecture optimization with voltage scaling, allowing a trade-off between silicon area and low-power operation. Architectural optimization enables supply voltages of the order of 1 V using standard CMOS technology. Several techniques can also be used to minimize the switched capacitance, including representation, optimizing signal correlations, minimizing spurious transitions, optimizing sequencing of operations, activity-driven power down, etc. The high- efficiency of DC-DC converter circuitry required for efficient, low-voltage and low-current level operation is described by Stratakos, Sullivan and Sanders. The application of various low-power techniques to a chip set for multimedia applications shows that orders-of-magnitude reduction in power consumption is possible. The book also features an analysis by Professor Meindl of the fundamental limits of power consumption achievable at all levels of the design hierarchy. Svensson, of ISI, describes emerging adiabatic switching techniques that can break the CV2f barrier and reduce the energy per computation at a fixed voltage. Srivastava, of AT&T, presents the application of aggressive shut-down techniques to microprocessor applications.

A silicon compiler is a software system which can automatically generate an integrated circuit from a user''s specification. Anatomy of a Silicon Compiler examines one such compiler in detail, covering the basic framework and design entry, the actual algorithms and libraries which are used, the approach to verification and testing, behavioral synthesis tools and several applications which demonstrate the system''s capabilities.

Low-Power CMOS Wireless Communications: A Wideband CDMA System Design focuses on the issues behind the development of a high-bandwidth, silicon complementary metal-oxide silicon (CMOS) low-power transceiver system for mobile RF wireless data communications. In the design of any RF communications system, three distinct factors must be considered: the propagation environment in question, the multiplexing and modulation of user data streams, and the complexity of hardware required to implement the desired link. None of these can be allowed to dominate. Coupling between system design and implementation is the key to simultaneously achieving high bandwidth and low power and is emphasized throughout the book. The material presented in Low-Power CMOS Wireless Communications: A Wideband CDMA System Design is the result of broadband wireless systems research done at the University of California, Berkeley. The wireless development was motivated by a much larger collaborative effort known as the Infopad Project, which was centered on developing a mobile information terminal for multimedia content - a wireless `network computer''. The desire for mobility, combined with the need to support potentially hundreds of users simultaneously accessing full-motion digital video, demanded a wireless solution that was of far lower power and higher data rate than could be provided by existing systems. That solution is the topic of this book: a case study of not only wireless systems designs, but also the implementation of such a link, down to the analog and digital circuit level.