Bashir M. Al-Hashimi is professor of Computer Engineering at the School of Electronics and Computer Science, University of Southampton, UK. Professor Al-Hashimi is Editor-in-Chief, IEE Proceedings: Computer and Digital Techniques. He is a Fellow of the IEE.

• Part 1: System-level designChapter 1: Multi-criteria decision making in embedded system designChapter 2: System-level performance analysis - the SymTA/S approachChapter 3: Analysis and optimisation of heterogeneous real-time embedded systemsChapter 4: Hardware/software partitioning of operating systems: focus on deadlock avoidanceChapter 5: Models of computation in the design processChapter 6: Architecture description languages for programmable embedded systemsPart 2: Embedded softwareChapter 7: Concurrent models of computation for embedded softwareChapter 8: Retargetable compilers and architecture exploration for embedded processorsChapter 9: Software power optimisationPart 3: Power reduction and managementChapter 10: Power-efficient data management for dynamic applicationsChapter 11: Low power system scheduling, synthesis and displaysChapter 12: Power minimisation techniques at the RT-level and belowChapter 13: Leakage power analysis and reduction for nano-scale circuitsPart 4: Reconfigurable computingChapter 14: Reconfigurable computing: architectures and design methodsPart 5: Architectural synthesisChapter 15: CAD tools for embedded analogue circuits in mixed-signal integrated Systems-on-ChipChapter 16: Clock-less circuits and system synthesisPart 6: Network-on-chipChapter 17: Network-on-chip architectures and design methodsChapter 18: Asynchronous on-chip networksPart 7: Simulation and verificationChapter 19: Covalidation of complex hardware/software systemsChapter 20: Hardware/software cosimulation from interface perspectiveChapter 21: System-level validation using formal techniquesPart 8: Manufacturing testChapter 22: Efficient modular testing and test resource partitioning for core-based SoCsChapter 23: On-chip test infrastructure design for optimal multi-site testingChapter 24: High-resolution flash time-to-digital conversion and calibration for system-on-chip testingChapter 25: Yield and reliability prediction for DSM circuits

Bashir M. Al-Hashimi is professor of Computer Engineering at the School of Electronics and Computer Science, University of Southampton, UK. Professor Al-Hashimi is Editor-in-Chief, IEE Proceedings: Computer and Digital Techniques. He is a Fellow of the IEE.

• Part 1: System-level designChapter 1: Multi-criteria decision making in embedded system designChapter 2: System-level performance analysis - the SymTA/S approachChapter 3: Analysis and optimisation of heterogeneous real-time embedded systemsChapter 4: Hardware/software partitioning of operating systems: focus on deadlock avoidanceChapter 5: Models of computation in the design processChapter 6: Architecture description languages for programmable embedded systemsPart 2: Embedded softwareChapter 7: Concurrent models of computation for embedded softwareChapter 8: Retargetable compilers and architecture exploration for embedded processorsChapter 9: Software power optimisationPart 3: Power reduction and managementChapter 10: Power-efficient data management for dynamic applicationsChapter 11: Low power system scheduling, synthesis and displaysChapter 12: Power minimisation techniques at the RT-level and belowChapter 13: Leakage power analysis and reduction for nano-scale circuitsPart 4: Reconfigurable computingChapter 14: Reconfigurable computing: architectures and design methodsPart 5: Architectural synthesisChapter 15: CAD tools for embedded analogue circuits in mixed-signal integrated Systems-on-ChipChapter 16: Clock-less circuits and system synthesisPart 6: Network-on-chipChapter 17: Network-on-chip architectures and design methodsChapter 18: Asynchronous on-chip networksPart 7: Simulation and verificationChapter 19: Covalidation of complex hardware/software systemsChapter 20: Hardware/software cosimulation from interface perspectiveChapter 21: System-level validation using formal techniquesPart 8: Manufacturing testChapter 22: Efficient modular testing and test resource partitioning for core-based SoCsChapter 23: On-chip test infrastructure design for optimal multi-site testingChapter 24: High-resolution flash time-to-digital conversion and calibration for system-on-chip testingChapter 25: Yield and reliability prediction for DSM circuits

Bashir M. Al-Hashimi is professor of Computer Engineering at the School of Electronics and Computer Science, University of Southampton, UK. Professor Al-Hashimi is Editor-in-Chief, IEE Proceedings: Computer and Digital Techniques. He is a Fellow of the IEE.

• Part 1: System-level designChapter 1: Multi-criteria decision making in embedded system designChapter 2: System-level performance analysis - the SymTA/S approachChapter 3: Analysis and optimisation of heterogeneous real-time embedded systemsChapter 4: Hardware/software partitioning of operating systems: focus on deadlock avoidanceChapter 5: Models of computation in the design processChapter 6: Architecture description languages for programmable embedded systemsPart 2: Embedded softwareChapter 7: Concurrent models of computation for embedded softwareChapter 8: Retargetable compilers and architecture exploration for embedded processorsChapter 9: Software power optimisationPart 3: Power reduction and managementChapter 10: Power-efficient data management for dynamic applicationsChapter 11: Low power system scheduling, synthesis and displaysChapter 12: Power minimisation techniques at the RT-level and belowChapter 13: Leakage power analysis and reduction for nano-scale circuitsPart 4: Reconfigurable computingChapter 14: Reconfigurable computing: architectures and design methodsPart 5: Architectural synthesisChapter 15: CAD tools for embedded analogue circuits in mixed-signal integrated Systems-on-ChipChapter 16: Clock-less circuits and system synthesisPart 6: Network-on-chipChapter 17: Network-on-chip architectures and design methodsChapter 18: Asynchronous on-chip networksPart 7: Simulation and verificationChapter 19: Covalidation of complex hardware/software systemsChapter 20: Hardware/software cosimulation from interface perspectiveChapter 21: System-level validation using formal techniquesPart 8: Manufacturing testChapter 22: Efficient modular testing and test resource partitioning for core-based SoCsChapter 23: On-chip test infrastructure design for optimal multi-site testingChapter 24: High-resolution flash time-to-digital conversion and calibration for system-on-chip testingChapter 25: Yield and reliability prediction for DSM circuits