Ricardo Reis – författare

Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault tolerant techniques for programmable logic applications.

Design of Systems on a Chip: Design&Test is the second of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the compilations of tutorials presented at workshops in the recent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip. In particular this second book include contributions on three different, but complementary axes: core design, computer-aided design tools and test methods. A collection of chapters deal with the heterogeneity aspect of core designs, showing the diversity of parts that may share the same substrate in a state-of-the-art system on a chip. The second part of the book discusses CAD in three different levels of design abstraction, from system level to physical design. The third part deals with test methods. The topic is addressed from different viewpoints: in terms of chip complexity, test is discussed from the core and system prospective; in terms of signal heterogeneity, the digital, mixed-signal and microsystem prospective are considered.

Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault toleranttechniques for programmable logic applications.

An incisive overview of the macroeconomics of financial crises—essential reading for students and policy experts alikeWith alarming frequency, modern economies go through macro-financial crashes that arise from the financial sector and spread to the broader economy, inflicting deep and prolonged recessions. A Crash Course on Crises brings together the latest cutting-edge economic research to identify the seeds of these crashes, reveal their triggers and consequences, and explain what policymakers can do about them.Each of the book’s ten self-contained chapters introduces readers to a key economic force and provides case studies that illustrate how that force was dominant. Markus Brunnermeier and Ricardo Reis show how the run-up phase of a crisis often occurs in ways that are preventable but that may go unnoticed and discuss how debt contracts, banks, and a search for safety can act as triggers and amplifiers that drive the economy to crash. Brunnermeier and Reis then explain how monetary, fiscal, and exchange-rate policies can respond to crises and prevent them from becoming persistent.With case studies ranging from Chile in the 1970s to the COVID-19 pandemic, A Crash Course on Crises synthesizes a vast literature into ten simple, accessible ideas and illuminates these concepts using novel diagrams and a clear analytical framework.

Radiation Effects on Embedded Systems aims at providing the reader with the major guidelines for coping with radiation effects on components supposed to be included in today’s applications devoted to operate in space, but also in the atmosphere at high altitude or at ground level. It contains a set of chapters based on the tutorials presented at the International School on Effects of Radiation on Embedded Systems for Space Applications (SERESSA) that was held in Manaus, Brazil, from 20 to 25 November 2005.

This book will provide all IC engineers with useful information regarding outside (environmental) influences on their designs and is an excellent reference.