Analog Circuits and Signal Processing – serie

Current-mode circuits, where information is represented by the branch currents of the circuits rather than the nodal voltages as of voltage-mode circuits, possess many unique and attractive characteristics over their voltage-mode counterparts including a small nodal time constant, high current swing in the presence of a low supply voltage, reduced distor­ tion, a low input impedance, a high output impedance, less sensitive to switching noise, and better ESD immunity. CMOS current-mode circuits have found increasing applications in telecommunication sys­ tems, instrumentation, analog signal processing, multiprocessors, high­ speed computer interfaces, and the backplane of complex electronic sys­ tems. This book deals with the analysis and design of continuous-time CMOS current-mode circuits for data communications over wire chan­ nels. CMOS current-mode sampled-data networks, such as switch- current circuits, and current-mode logic circuits, are excluded. The book is organized as the followings : Chapter 1 examines the distinct characteristics of ideal voltage-mode and current-mode circuits. The topology duaUty of these two classes of circuits is investigated using the concept of inter-reciprocity and adjoint network. A critical comparison of the input and output impedances, bandwidth, slew rate, propagation delay, signal swing, supply voltage sensitivity, and ESD sensitivity of voltage-mode and current-mode cir­ cuits is provided. Chapter 2 investigates design techniques that improve the perfor­ mance of low-voltage current-mode circuits including input impedance reduction, output impedance boosting, bandwidth enhancement, mis­ match compensation, power consumption reduction, and swing improve­ ment. Chapter 3 investigates the modeling of wire channels.

In "The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits", we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files found on extras-springer.com  allow redoing the tests.

Analog design at ultra-low supply voltages is an important challenge for the semiconductor research community and industry.Analog Circuit Design Techniques at 0.5V covers challenges for the design of MOS analog and RF circuits at a 0.5 V power supply voltage. All design techniques presented are true low voltage techniques - all nodes in the circuits are within the power supply rails. The circuit implementations of body and gate input fully differential amplifiers are also discussed. These building blocks enable us to build continuous-time filters, track-and-hold circuits, and continuous-time sigma delta modulators.Current books on low voltage analog design typically cover techniques for supply voltages down to approximately 1V. This book presents novel ideas and results for operation from much lower supply voltages and the techniques presented are basic circuit techniques that are widely applicable beyond the scope of the presented examples.Analog Circuit Design Techniques at 0.5V is written for analog circuit designers and researchers as well as graduate students studying semiconductors and integrated circuit design.

Advanced Design Techniques for RF Power Amplifiers' main aim is to provide the reader with a deep analysis of theoretical aspects, modelling, and design strategies of RF high-efficiency power amplifiers. Advanced Design Techniques for RF Power Amplifiers begins with an analytical review of current state of the problem. Then it moves to the theoretical analysis of BJT class-F power amplifier near transition frequency and presents the necessary realization conditions. The next part concerns the practical verification and demonstration of the theoretical results. It is followed by the part devoted to the output networks of high-efficiency power ampifiers. The novel type of photonic band-gap structure providing improved characteristics both in the pass and stop bands is proposed. Finally, the fifth-harmonic peaking class F power amplifier design based on the above structure is presented.

CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design starts with a tutorial presentation of the fundamentals of low-pass sigma-delta modulators, their applications, and their most common architectures. It then presents an exhaustive analysis of SC circuit errors with a twofold outcome. On the one hand, compact expressions are derived to support design plans and quick top-down design. On the other, detailed behavioral models are presented to support accurate verification. This set of models allows the designer to determine the required specifications for the different modulator building blocks and form the basis of a systematic design approach. The book is completed in subsequent chapters with the detailed presentation of three high-performance modulator ICs: the first two are intended for DSL-like applications, whereas the third one is intended for automotive sensors.CMOS Cascade Sigma-Delta Modulators forSensors and Telecom: Error Analysis and Practical Design contains highly valuable information that is structured to give the reader the necessary insight on how to design SC sigma-delta modulators.

In the market of wireless communication, high data-rate transmission and high spectral efficiency have been the trend. The IEEE 802.11 a/g standards working at 5GHz/2.4GHz ISM bands can support data rate up to 54Mbits/s using OFDM modulation. The newly proposed 802.11n technology now uses 64-QAM to achieve higher spectral efficiency. The DVB and many other systems will also use QAM for its data transmission.The cost of achieving this higher spectral efficiency using higher order QAM is that the transmitter and receiver requires a higher signal to noise ratio (SNR) with the same level of error rate performance (relative to a baseline BPSK, QPSK and other systems). One of the dominant vectors on SNR degradation is I/Q image rejection (I/Q gains and phases imbalance).There are a lot of factors that degrade the matching of gains and phases between I/Q signals: the instinct layout mismatch, the random mismatch of the devices, the different temperatures over the I/Q signal paths. IQ Calibration Techniques For CMOS Radio Transceivers describes a fully-analog compensation technique without baseband circuitry to control the calibration process. This book will use an 802.11g transceiver design as an example to give a detailed description on the I/Q gains and phases imbalance auto-calibration mechanism.

RF Power Amplifiers for Mobile Communications fits in the quest for fully integrated CMOS transceivers. The book tackles both high efficiency and high linearity PA design in low-voltage CMOS, and has a strong emphasis on theory, design and implementation. The book is conceived as a design guide for those actively involved in the design of CMOS wireless transceivers.RF Power Amplifiers for Mobile Communications starts from the basic theory of power amplification from the viewpoint of CMOS integration. The design of switching RF power amplifiers in CMOS is explored and CMOS PA design at low supply voltage using parallel amplification is discussed. Combining both efficiency and linearity is one of the major issues in CMOS PA design for wireless and mobile communications and is subsequently tackled. Different linearization techniques and approaches are discussed and polar modulation is clarified in greater detail. Finally, two CMOS PAimplementations are thoroughly covered. RF Power Amplifiers for Mobile Communications offers the reader an intuitive insight in Power Amplification as well as the necessary mathematical background. The book is essential reading for RF design engineers and researchers in the field and is also suitable as a text book for an advanced course on the subject.

Adaptive radio transceivers require a comprehensive theoretical framework in order to optimize their performance. Adaptive Low-Power Circuits for Wireless Communications provides this framework with a discussion of joint optimization of Noise Figure and Input Intercept Point in receiver systems. Original techniques to optimize voltage controlled oscillators and low-noise amplifiers to minimize their power consumption while maintaining adequate system performance are also provided. The experimental results presented at the end of the book confirm the utility of the proposed techniques.

The low cost and direct digital output of CMOS smart temperature sensors are important advantages compared to conventional temperature sensors. This book addresses the main problem that nevertheless prevents widespread - plication of CMOS smart temperature sensors: their relatively poor absolute accuracy. Several new techniques are introduced to improve this accuracy. The effectiveness of these techniques is demonstrated using three prototypes. ? The ?nal prototype achieves an inaccuracy of±0.1 C over the military t- perature range, which is a signi?cant improvement in the state of the art. Since smart temperature sensors have been the subject of academic and industrial research for more than two decades, an overview of existing knowledge and techniques is also provided throughout the book. Inthisintroductorychapter,themotivationandobjectivesofthisworkare- scribed. ThisisfollowedbyareviewofthebasicoperatingprinciplesofCMOS smart temperature sensors, and a brief overview of previous work. The ch- lenges are then described that need to be met in order to improve the accuracy of CMOS smart temperature sensors while maintaining their cost advantage. Finally, the structure of the rest of the book is introduced.

Low-Frequency Noise in Advanced CMOS Devices begins with an introduction to noise, describing the fundamental noise sources and basic circuit analysis. The characterization of low-frequency noise is discussed in detail and useful practical advice is given. The various theoretical and compact low-frequency (1/f) noise models in MOS transistors are treated extensively providing an in-depth understanding of the low-frequency noise mechanisms and the potential sources of the noise in MOS transistors. Advanced CMOS technology including nanometer scaled devices, strained Si, SiGe, SOI, high-k gate dielectrics, multiple gates and metal gates are discussed from a low-frequency noise point of view. Some of the most recent publications and conference presentations are included in order to give the very latest view on the topics. The book ends with an introduction to noise in analog/RF circuits and describes how the low-frequency noise can affect these circuits.

The intention of this book is to address a number of timely, performance-critical issues within the field of short-distance optical communications, from a circuit designer’s perspective. It discusses the major trade-offs the designer has to deal with in the development of monolithically integrated receivers in CMOS technologies. As such, it is based on Dr. Muller’s doctoral dissertation entitled “A Standard CMOS Multi-Channel Single-Chip Receiver for Multi-Gigabit Optical Data Communications”, subm- ted to the School of Engineering of the École Polytechnique Fédérale de Lausanne (EPFL) in May 2006. The dissertation material has been enhanced by the presentation of a number of alternative design approaches and circuit topologies, providing exhaustive coverage of the state of the art in optical sho- distance receiver circuit design. The need for a new processor input/output (I/O) interface paradigm is dictated by ongoing te- nology scaling and the advent of multi-core systems. Indeed, each new generation of microprocessors and digital signal processors provides higher computing power and data throughput, whereas the available bandwidth of the I/O interfaces is subject to much slower growth. Moving beyond - coming serial links to an optical data link paradigm for very short-distance (board-to-board and chip-- chip communications allows for considerable I/O interface bandwidth enhancement. Fully integrated silicon CMOS receivers are considered to be the technology of choice to lead this solution to economic success, because monolithic integration results in lower volume-manufacturing cost, improved yield and reduced assembly and test expenses.

Recently, wireless LAN standards have emerged in the market. Those standards operate in various frequency ranges. To reduce component count, it is of importance to design a multi-mode frequency synthesizer that serves all wireless LAN standards including 802.11a, 802.11b and 802.11g standards. With different specifications for those standards, designing integer-based phase-locked loop frequency synthesizers can not be achieved. Fractional-N frequency synthesizers offer the solution required for a common multi-mode local oscillator. Those fractional-N synthesizers are based on delta-sigma modulators which in combination with a divider yield the fractional division required for the desired frequency of interest. In CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications, the authors outline detailed design methodology for fast frequency hopping synthesizers for RF and wireless communications applications. Great emphasis on fractional-N delta-sigma based phase locked loops from specifications, system analysis and architecture planning to circuit design and silicon implementation. The book describes an efficient design and characterization methodology that has been developed to study loop trade-offs in both open and close loop modelling techniques. This is based on a simulation platform that incorporates both behavioral models and measured/simulated sub-blocks of the chosen frequency synthesizer. The platform predicts accurately the phase noise, spurious and switching performance of the final design. Therefore excellent phase noise and spurious performance can be achieved while meeting all the specified requirements. The design methodology reduces the need for silicon re-spin enabling circuit designers to directly meet cost, performance and schedule milestones.The developed knowledge and techniques have been used in the successful design and implementation of two high speed multi-modefractional-N frequency synthesizers for the IEEE 801.11a/b/g standards. Both synthesizer designs are described in details.

At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture.In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability.

Broadband Opto-Electrical Receivers in Standard CMOS fits in the quest for integrated opto-electrical solutions, and focuses on the receiver front-end. To further reduce the cost, the cheapest technology is selected: standard CMOS, without any optical tricks or flavors. The emphasis is on the analysis, design and implementation of high-performance analog receiver circuits. Broadband Opto-Electrical Receivers in Standard CMOS starts from the basic fundamentals, necessary for the design of opto-electronic interface circuits. The book continues with an in-depth analysis of the photodiode, transimpedance amplifier (TIA) and limiting amplifier (LA). To thoroughly understand the light detection mechanisms in silicon, first a one-dimensional and second a two-dimensional model is developed. Analytical design equations are derived to guide the design of the amplifying circuits. For the TIA, the focus lies on the sensitivity-speed trade-off. For the LA, a high gain-bandwidth is pursued. Several practical design examples reveal the subtleties and challenges encountered during the design of high-performance analog circuits.Broadband Opto-Electrical Receivers in Standard CMOS covers the total design flow of monolithic CMOS optical receivers.All material is experimentally verified with several CMOS implementations, with ultimately a fully integrated Gbit/s optical receiver front-end including photodiode, TIA and LA. The book is essential reading for analog design engineers and researchers in the field and is also suitable as a text book for an advanced course on the subject.

The increasing performance of smart microsystems merging sensors, signal processing and wireless communication promises to have a pervasive impact during the coming decade. These autonomous microsystems nd applications in sport evaluation, health care, environmental monitoring and automotive s- tems. They gather data from the physical world, convert them to electrical form, compensate for interfering variables or non-linearities, and either act - rectly on them or transfer it to other systems. Most often, these sensor systems are developed for a speci c application. This approach leads to a high rec- rent design cost. A generic front-end architecture, where only the sensors and the microcontroller software are customized to the selected application, would reduce the costs signi cantly. This work presents a new generic architecture for autonomous sensor nodes. The modular design methodology provides a exible way to build a complete sensor interface out of con gurable blocks. The settings of these blocks can be optimized according to the varying needs of the application. Furthermore, the system can easily be expanded with new building blocks. The modular system is illustrated in a Generic Sensor Interface Chip (GSIC) for capa- tive sensors. Many con guration settings adapt the interface to a broad range of applications. The GSIC is optimized for ultra low power consumption. It achieves an ON-state current consumption of 40?A.

Switched capacitor (SC) techniques are well proven to be excellent candidates for implementing critical analogue functions with high accuracy, surpassing other analogue techniques when embedded in mixed-signal CMOS VLSI. Conventional SC circuits are primarily limited in accuracy by a) capacitor matching and b) the accuracy with which a differential amplifier can squeeze charge from one capacitor to another between clock periods. In Switched-Capacitor Techniques for High-Accuracy Filter and ADC Design, alternative SC techniques are proposed which allow the achievement of higher intrinsic analogue functional accuracy than previously possible in such application areas as analogue filter and ADC design. The design philosophy is to create the required functionality without relying on digital calibration or correction means but instead to develop methods which have reduced dependence on both component matching (especially capacitor matching) and parasitic effects (especially parasitic capacitance). However, the proposed techniques are just as amenable to further digital accuracy enhancement via calibration and/or correction as traditional methods. Two popular application areas are explored in the course of this book for exploitation of the proposed techniques, viz. SC filters and algorithmic ADCs - both cyclic and pipelined. Furthermore, efficient system level design procedures are explored in each of these two areas.The validity of the concepts developed and analyzed in Switched-Capacitor Techniques for High-Accuracy Filter and ADC Design has been demonstrated in practice with the design of CMOS SC bandpass filters and algorithmic ADC stages. For example, a 10.7MHz radio IF selectivity filter integrated in standard CMOS, employing the proposed methods, achieves an accuracy greater than ceramic filters. Another example is an ADC with better than 12-bit intrinsic accuracy, albeit capacitors with only 9-bits matching accuracy were used in the realization. The ADC architecture is also very robust and proven in an embedded digital VLSI application in the very newest 65nm CMOS. The power consumptions and silicon areas of the solutions proposed here are lower than other known solutions from the literature.

The prospect of initializing a network-ubiquitous society in the years to come has led to the development of multistandard-compliant wireless transceivers for seamless roaming among multiple networks. To ensure a commercial success of such a development, the manufacturing cost and power consumption of the system chips have to be minimized. The use of an advanced technology and a high level of integration have continued to be the most effective ways for cost and power minimization, given that wireless chips integrate large amounts of digital logic for computation. Regrettably, entering into the nanoelectronics era, the thinner transistor gate oxide implicates great challenges in the design of the analog front-ends. While a low-voltage supply is imposed to maintain device reliability, a relatively large threshold voltage is also necessitated to limit the leakage current. Thus, transceiver architectures and circuits which will befit future full integration of multistandard wireless transceivers in sub-1V nanoscale CMOS processes must be highly reconfigurable and robustly operational underneath a l- voltage supply. This book presents novel analog-baseband architectures and circuits that help realizing multistandard and low-voltage wireless transceivers. The main contents are presented from Chapter 2 to Chapter 6, as pictorially outlined in Figure 1. Chapter 1 overviews the current wireless-IC developments and presents the motivation and research objectives of this book. xi xii Preface Figure 1.

N this information era people are living in a society in which processing, ?ow and Iexchange of information are vital for their existence. Two major issues in such so- ety, which are related to ?ow and exchange of information, are connectivity and mobility. On one hand, computers and Internet provide connectivity and allow communication as well as fast access to large amounts of information. On the other hand, wireless techno- gies bring mobility. People can move and still be able to communicate and have access to various kind of information. Therefore, the functioning of an information society is unthinkable without the use of computers, Internet and wireless technologies. The exp- tations are that in the future they will merge into a unique system for communication, access to information as well as their exchange and processing. The era of wireless communications started in 1901, when Guglielmo Marconi s- cessfully transmitted radio signals across the Atlantic Ocean. From that moment up to now wireless communications experienced explosive growth and became the fastest growing ?eld in the engineering world. Pushed by customer requirements, new wireless techno- gies have been emerging very fast. Each new generation of wireless technologies have brought new features and more complexity. Pushed by market forces to reduce costs, the semiconductor industry has provided new technologies for solid-state circuits implem- tation. Fortunately at the same time with the cost reduction, performance of new te- nologies has been improving.

By the end of this decade, a 4G wireless terminal will be available that provides high quality multimedia, personalized services, and ubiquitous multi-standard broadband connectivity with a reasonable power consumption. In this context, a multi-band transceiver is needed that provides a high-level of programmability while keeping low design complexity and costs. Software Defined Radio (SDR) is the most promising technology to implement such a terminal as it enables multi-mode reception by tuning to any frequency band, by selecting any channel bandwidth, and by detecting any modulation. Baseband Analog Circuits for Software Defined Radio aims to describe the transition towards a Software Radio from the analog design perspective. As the original idea of a "full-digital" Software Radio is far from the state-of-art, an analog front-end is still needed to achieve a feasible implementation. Most of the existent front-end architectures are explored from the flexibility point of view. A complete overview of the actual state-of-art for reconfigurable transceivers is given in detail, focusing on the challenges imposed by flexibility in analog design.As far as the design of adaptive analog circuits is concerned, specifications like bandwidth, gain, noise, resolution and linearity should be programmable. The development of circuit topologies and architectures that can be easily reconfigured while providing a near optimal power/performance trade-offs is a key challenge. In this book, we tackle this challenge mainly for baseband analog circuits, i.e. amplifiers and filters, proposing efficient solutions that provide a high level of programmability. Measurements results validate the design strategies.

A comprehensive study of silicon-based distributed architectures in wideband circuits are presented in this book. Novel circuit architectures for ultra-wideband (UWB) wireless technologies are described. The book begins with an introduction of several transceiver architectures for UWB. The discussion then focuses on RF front-end of the UWB radio. Therefore, the book will be of interest to RF circuit designers and students.

“Design of high voltage xDSL line drivers in standard CMOS” fits in the quest for highly efficient fully integrated xDSL modems for central office applications. The book focusses on the line driver, the most demanding building block of the xDSL modem for lowering power. To reduce the cost, the cheapest technology is selected: standard CMOS, without any extra process options to increase the nominal supply voltage. The emphasis lies on the analysis, design and implementation of high voltage highly efficient line drivers in mainstream CMOS.“Design of high voltage xDSL line drivers in standard CMOS” covers the total design flow of monolithic CMOS high voltage circuits. The book is essential reading for analog design engineers and researchers in the field and is also suitable as a text book for an advanced course on the subject.

As the miniaturization of semiconductor technology continues, electronic s- tems on chips o?er a more extensive and more complex functionality with better performance, higher frequencies and less power consumption. Whereas digital designers can take full advantage of the availability of design auto- tiontoolstobuildhugesystems,thelackofsupportbycomputerprogramsfor di?erent abstraction levels makes analog design a time-consuming handcraft which limits the possibilities to implement large systems. Various approaches for?ndingoptimalvaluesfortheparametersofanalogcells,likeopamps,have been investigated since the mid-1980s, and they have made their entrance in commercial applications. However, a larger impact on the performance is - pected if tools are developed which operate on a higher abstraction level and consider multiple architectural choices to realize a particular functionality. In this book, the opportunities, conditions, problems, solutions and systematic methodologies for this new generation of analog CAD tools are examined. Theoutlineofthisbookisasfollows. Inthe?rstpart,thecharacteristicsof the analog design process are systematically analyzed and several approaches for automated analog synthesis are summarized. Comparison of their prop- ties with the requirements for high-level synthesis of analog and mixed-signal systems results in a new design paradigm: the high-level design ?ow based on generic behavior. This design approach involves a modeling strategy using generic behavioral models and a synthesis strategy leading to the exploration of a heterogeneous design space containing di?erent architectures. The modeling strategy is further elaborated in Part II.

Realizing maximum performance from high bit-rate and RF circuits requires close attention to IC technology, circuit-to-circuit interconnections (i.e., the ‘interconnect’) and circuit design. Circuit and Interconnet Design for RF and High Bit-rate Applications covers each of these topics from theory to practice, with sufficient detail to help you produce circuits that are ‘first-time right’. A thorough analysis of the interplay between on-chip circuits and interconnects is presented, including practical examples in high bit-rate and RF applications. Optimum interconnect geometries for the distribution of RF signals are described, together with simple models for standard interconnect geometries that capture characteristic impedance and propagation delay across a broad frequency range. The analyses also covers single-ended and differential geometries, so that the designer can incorporate the effects of interconnections as soon as estimated interconnect lengths are available. Application of interconnect design is illustrated using a 12.5 Gb/s crosspoint switch example taken from a volume production part.

High-Resolution IF-to-Baseband SigmaDelta ADC for Car Radios addresses the theory, system level design and circuit implementation of a high-resolution continuous-time IF-to-baseband quadrature SigmaDelta ADC. The target application of this ADC is in AM/FM/IBOC car radios. The ADC achieves a dynamic range of 118dB, which eliminates the need for an IF VGA or AM channel filter in car radios.

Substrate noise coupling in integrated circuits (ICs) is the process by which int- ference signals in the form of voltage and current glitches cause parasitic currents to ?ow in the silicon substrate to various parts of the IC. The source of such glitches and parasitic currents could be from the switching noise of high speed digital clocks on the same chip. In RF and mixed signal ICs the switching noise is coupled to sensitive analog and RF nodes in the IC causing degradation in performance that could severely impact the yield. Thus, overcoming substrate coupling is a key issue in successful “system on chip” ?rst-pass integration where RF and mixed signal blocks, high speed digital I/O interface are integrated with digital signal proce- ing algorithms on the same chip. This is particularly true as we move to sub-90 nanometer system on chip integration. In this book a substrate aware design ?ow is built, calibrated to silicon and used as part of the design and validation ?ows to uncover and ?x substrate coupling problems in RF ICs. The ?ow is used to develop a comprehensive RF substrate noise isolation design guide to be used by RF designers during the ?oor planning, circuit design and validation phases. This will allow designers to optimize the - sign, maximize noise isolation and protect sensitive analog/RF blocks from being degraded by substrate noise coupling.

Low Power UWB CMOS Radar Sensors deals with the problem of designing low cost CMOS radar sensors. The radar sensor uses UWB signals in order to obtain a reasonable target separation capability, while maintaining a maximum signal frequency below 2 GHz. This maximum frequency value is well within the reach of current CMOS technologies. The use of UWB signals means that most of the methodologies used in the design of circuits and systems that process narrow band signals, can no longer be applied. Low Power UWB CMOS Radar Sensors provides an analysis between the interaction of UWB signals, the antennas and the processing circuits. This analysis leads to some interesting conclusions on the types of antennas and types of circuits that should be used. A methodology to compare the noise performance of UWB processing circuits is also derived. This methodology is used to analyze and design the constituting circuits of the radar transceiver. In order to validate the design methodology a CMOS prototype is designed and experimentally evaluated.

Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input.2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.

Modern RF receivers and transmitters require quadrature oscillators with accurate quadrature and low phase-noise. Existing literature is dedicated mainly to single oscillators, and is strongly biased towards LC oscillators. This book is devoted to quadrature oscillatorsand presents adetailed comparative study ofLC and RCosc- lators, both at architectural and at circuit levels. It is shown that in cross-coupled RC oscillators both the quadrature error and phase-noise are reduced, whereas in LC - cillators the coupling decreases the quadrature error, but increases the phase-noise. Thus, quadrature RC oscillators can be a practical alternative to LC oscillators, - pecially when area and cost are to be minimized. The main topics of the book are: cross-coupled LC quasi-sinusoidal oscillators, cross-coupled RC relaxation oscillators, a quadrature RC oscillator-mixer, and t- integrator oscillators. The effect of mismatches on the phase-error and the pha- noise are thoroughly investigated. The book includes many experimental results, obtained from different integrated circuit prototypes, in the GHz range. A structured design approach is followed: a technology independent study, with ideal blocks, is performed initially, and then the circuit level design is addressed. This book can be used in advanced courses on RF circuit design. In addition to post-graduate students and lecturers, this book will be of interest to design engineers and researchers in this area.

Structured Analog CMOS Design describes a structured analog design approach that makes it possible to simplify complex analog design problems and develop a design strategy that can be used for the design of large number of analog cells. It intentionally avoids treating the analog design as a mathematical problem, developing a design procedure based on the understanding of device physics and approximations that give insight into parameter interdependences.The basic design concept consists in analog cell partitioning into the basic analog structures and sizing of these basic analog structures in a predefined procedural design sequence. The procedural design sequence ensures the correct propagation of design specifications, the verification of parameter limits and the local optimization loops. The proposed design procedure is also implemented as a CAD tool that follows this book.